From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8 Date: Mon, 7 Jul 2014 23:23:32 +0200 Message-ID: <20140707212332.GK17271@phenom.ffwll.local> References: <1404485433-4488-1-git-send-email-przanoni@gmail.com> <1404485433-4488-2-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f51.google.com (mail-wg0-f51.google.com [74.125.82.51]) by gabe.freedesktop.org (Postfix) with ESMTP id 35DF289E59 for ; Mon, 7 Jul 2014 14:23:22 -0700 (PDT) Received: by mail-wg0-f51.google.com with SMTP id y10so264420wgg.22 for ; Mon, 07 Jul 2014 14:23:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1404485433-4488-2-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > If we enable unclaimed register reporting on Gen 8, we will discover > that the IRQ registers for pipes B and C are also on the power well, > so writes to them when the power well is disabled result in unclaimed > register errors. > > Also, hsw_power_well_post_enable() already takes care of re-enabling > them once the power well is enabled. > > Testcase: igt/pm_rpm/rte > Signed-off-by: Paulo Zanoni Hm, shouldn't we split this into only setting up pipe A here and the pipe B stuff once we fire up the power well? I just want to avoid duplicating logic all over the place ... -Daniel > --- > drivers/gpu/drm/i915/i915_irq.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 1c1ec22..2e116e9d 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3193,7 +3193,9 @@ static void gen8_irq_reset(struct drm_device *dev) > gen8_gt_irq_reset(dev_priv); > > for_each_pipe(pipe) > - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); > + if (intel_display_power_enabled(dev_priv, > + POWER_DOMAIN_PIPE(pipe))) > + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); > > GEN5_IRQ_RESET(GEN8_DE_PORT_); > GEN5_IRQ_RESET(GEN8_DE_MISC_); > @@ -3526,8 +3528,11 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; > > for_each_pipe(pipe) > - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], > - de_pipe_enables); > + if (intel_display_power_enabled(dev_priv, > + POWER_DOMAIN_PIPE(pipe))) > + GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, > + dev_priv->de_irq_mask[pipe], > + de_pipe_enables); > > GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); > } > -- > 2.0.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch