From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8
Date: Tue, 8 Jul 2014 16:58:03 +0200 [thread overview]
Message-ID: <20140708145803.GJ17271@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGQvMRh3Bsmqgwd4Vs0Dt6_zNAMdJF97=S-jifuHsrAObg@mail.gmail.com>
On Tue, Jul 08, 2014 at 11:15:03AM -0300, Paulo Zanoni wrote:
> 2014-07-07 18:23 GMT-03:00 Daniel Vetter <daniel@ffwll.ch>:
> > On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> If we enable unclaimed register reporting on Gen 8, we will discover
> >> that the IRQ registers for pipes B and C are also on the power well,
> >> so writes to them when the power well is disabled result in unclaimed
> >> register errors.
> >>
> >> Also, hsw_power_well_post_enable() already takes care of re-enabling
> >> them once the power well is enabled.
> >>
> >> Testcase: igt/pm_rpm/rte
> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Hm, shouldn't we split this into only setting up pipe A here and the pipe
> > B stuff once we fire up the power well?
> >
>
> No because these functions might be called when the power wells are
> already enabled.
Hm, where does this still happen? bdw has power well support and chv has a
different display block ...
This code changed too often and I have no idea any more what's up and
what's down here ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-07-08 14:57 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-04 14:50 [PATCH 0/5] BDW unclaimed registers Paulo Zanoni
2014-07-04 14:50 ` [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8 Paulo Zanoni
2014-07-07 21:23 ` Daniel Vetter
2014-07-08 14:15 ` Paulo Zanoni
2014-07-08 14:58 ` Daniel Vetter [this message]
2014-07-10 19:31 ` Paulo Zanoni
2014-07-15 16:42 ` Rodrigo Vivi
2014-07-04 14:50 ` [PATCH 2/5] drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW Paulo Zanoni
2014-07-15 16:43 ` Rodrigo Vivi
2014-07-04 14:50 ` [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable Paulo Zanoni
2014-07-15 17:25 ` Rodrigo Vivi
2014-07-04 14:50 ` [PATCH 4/5] drm/i915: reorganize the unclaimed register detection code Paulo Zanoni
2014-07-07 21:34 ` Daniel Vetter
2014-07-15 19:17 ` Rodrigo Vivi
2014-07-04 14:50 ` [PATCH 5/5] drm/i915: BDW can also detect unclaimed registers Paulo Zanoni
2014-07-15 19:20 ` Rodrigo Vivi
2014-07-16 13:57 ` Daniel Vetter
2014-07-16 20:49 ` [PATCH 1/2] drm/i915: reorganize the unclaimed register detection code Paulo Zanoni
2014-07-16 20:49 ` [PATCH 2/2] drm/i915: BDW can also detect unclaimed registers Paulo Zanoni
2014-07-17 8:33 ` Daniel Vetter
2014-08-26 10:22 ` [PATCH 1/2] drm/i915: reorganize the unclaimed register detection code Chris Wilson
2014-08-26 12:17 ` Paulo Zanoni
2014-08-26 12:42 ` Chris Wilson
2014-08-26 13:04 ` Paulo Zanoni
2014-08-26 13:18 ` Chris Wilson
2014-08-26 13:29 ` Paulo Zanoni
2014-08-26 13:34 ` Daniel Vetter
2014-08-26 13:46 ` Chris Wilson
2014-08-26 14:08 ` Daniel Vetter
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