From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 07/10] drm/i915: HWS must be in the mappable region for g33 Date: Tue, 8 Jul 2014 21:07:31 +0200 Message-ID: <20140708190731.GL17271@phenom.ffwll.local> References: <1404423186-2019-1-git-send-email-rodrigo.vivi@intel.com> <1404423186-2019-8-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 560776E5C0 for ; Tue, 8 Jul 2014 12:07:21 -0700 (PDT) Received: by mail-wg0-f50.google.com with SMTP id x13so5458730wgg.9 for ; Tue, 08 Jul 2014 12:07:20 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1404423186-2019-8-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 03, 2014 at 05:33:03PM -0400, Rodrigo Vivi wrote: > From: Chris Wilson > = > On g33, the documentation states > = > "HWS_PGA: > Format =3D Bits 28:12 of graphics memory address (bits 31:29 MBZ)." > = > which translates to that the address of the HWS must be below 256MiB, > which is conveniently the mappable aperture. > = > This also appears to be true (but not documented as so) for gen4 and > gen5. To generalise we force it into the low mappable region for all > non-LLC platforms. If we locate the HWS at the top of the GTT the > machine will hard hang during boot (fails on pnv, gm45, ilk and byt, > but works on snb, ivb, hsw). > = > v2: Add comments to explain why use PIN_MAPPABLE even though we have > no intention of mapping the object. (Ville) > = > Signed-off-by: Chris Wilson > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 2faef26..f49a3dd 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1331,6 +1331,7 @@ static int init_status_page(struct intel_engine_cs = *ring) > struct drm_i915_gem_object *obj; > = > if ((obj =3D ring->status_page.obj) =3D=3D NULL) { > + unsigned flags; > int ret; > = > obj =3D i915_gem_alloc_object(ring->dev, 4096); > @@ -1343,7 +1344,20 @@ static int init_status_page(struct intel_engine_cs= *ring) > if (ret) > goto err_unref; > = > - ret =3D i915_gem_obj_ggtt_pin(obj, 4096, 0); > + flags =3D 0; > + if (!HAS_LLC(ring->dev)) > + /* On g33, we cannot place HWS above 256MiB, so > + * restrict its pinning to the low mappable arena. > + * Though this restriction is not documented for > + * gen4, gen5, or byt, they also behave similarly > + * and hang if the HWS is placed at the top of the > + * GTT. To generalise, it appears that all !llc > + * platforms have issues with us placing the HWS > + * above the mappable region (even though we never > + * actualy map it). > + */ > + flags |=3D PIN_MAPPABLE; > + ret =3D i915_gem_obj_ggtt_pin(obj, 4096, flags); > if (ret) { > err_unref: > drm_gem_object_unreference(&obj->base); > -- = > 1.9.0 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch