* [RFC 1/1] drm/i915: Power gating display wells during i915_pm_suspend @ 2014-07-11 15:18 sagar.a.kamble 2014-07-11 16:14 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: sagar.a.kamble @ 2014-07-11 15:18 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni, Daniel Vetter, Borun Fu, Sagar Kamble From: Borun Fu <borun.fu@intel.com> On VLV, after i915_pm_suspend display power wells are staying power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" Display is staing D0 State. There might be better way/place to power gate these wells. Also, we need to make sure that if wells are power gated due to DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_display.c | 4 ---- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 83cb43a..a83a48e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -491,6 +491,9 @@ static int i915_drm_freeze(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc; pci_power_t opregion_target_state; + struct intel_crtc *intel_crtc; + enum intel_display_power_domain domain; + unsigned long domains; /* ignore lid events during suspend */ mutex_lock(&dev_priv->modeset_restore_lock); @@ -529,6 +532,14 @@ static int i915_drm_freeze(struct drm_device *dev) drm_modeset_lock_all(dev); for_each_crtc(dev, crtc) { dev_priv->display.crtc_disable(crtc); + + intel_crtc = to_intel_crtc(crtc); + if (!HAS_DDI(dev)) { + domains = intel_crtc->enabled_power_domains; + for_each_power_domain(domain, domains) + intel_display_power_put(dev_priv, domain); + intel_crtc->enabled_power_domains = 0; + } } drm_modeset_unlock_all(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 47c8ec1..1d75007 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -179,6 +179,10 @@ enum hpd_pin { list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ if ((intel_connector)->base.encoder == (__encoder)) +#define for_each_power_domain(domain, mask) \ + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ + if ((1 << (domain)) & (mask)) + struct drm_i915_private; struct i915_mmu_object; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 72abc0b..b29d417 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4300,10 +4300,6 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) I915_WRITE(BCLRPAT(crtc->pipe), 0); } -#define for_each_power_domain(domain, mask) \ - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ - if ((1 << (domain)) & (mask)) - enum intel_display_power_domain intel_display_port_power_domain(struct intel_encoder *intel_encoder) { -- 1.8.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RFC 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-11 15:18 [RFC 1/1] drm/i915: Power gating display wells during i915_pm_suspend sagar.a.kamble @ 2014-07-11 16:14 ` Daniel Vetter 2014-07-12 4:32 ` [RFC v2 " sagar.a.kamble 0 siblings, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2014-07-11 16:14 UTC (permalink / raw) To: sagar.a.kamble; +Cc: Paulo Zanoni, Daniel Vetter, intel-gfx, Borun Fu On Fri, Jul 11, 2014 at 08:48:43PM +0530, sagar.a.kamble@intel.com wrote: > From: Borun Fu <borun.fu@intel.com> > > On VLV, after i915_pm_suspend display power wells are staying > power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" > Display is staing D0 State. There might be better way/place to power gate > these wells. Also, we need to make sure that if wells are power gated due to > DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 4 ++++ > drivers/gpu/drm/i915/intel_display.c | 4 ---- > 3 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 83cb43a..a83a48e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -491,6 +491,9 @@ static int i915_drm_freeze(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > struct drm_crtc *crtc; > pci_power_t opregion_target_state; > + struct intel_crtc *intel_crtc; > + enum intel_display_power_domain domain; > + unsigned long domains; > > /* ignore lid events during suspend */ > mutex_lock(&dev_priv->modeset_restore_lock); > @@ -529,6 +532,14 @@ static int i915_drm_freeze(struct drm_device *dev) > drm_modeset_lock_all(dev); > for_each_crtc(dev, crtc) { > dev_priv->display.crtc_disable(crtc); > + > + intel_crtc = to_intel_crtc(crtc); > + if (!HAS_DDI(dev)) { The HAS_DDI check is no longer required, just merged the patch for that. And I think we should extract an intel_crtc_disable helper to share it with the dpms off code. -Daniel > + domains = intel_crtc->enabled_power_domains; > + for_each_power_domain(domain, domains) > + intel_display_power_put(dev_priv, domain); > + intel_crtc->enabled_power_domains = 0; > + } > } > drm_modeset_unlock_all(dev); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 47c8ec1..1d75007 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -179,6 +179,10 @@ enum hpd_pin { > list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ > if ((intel_connector)->base.encoder == (__encoder)) > > +#define for_each_power_domain(domain, mask) \ > + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > + if ((1 << (domain)) & (mask)) > + > struct drm_i915_private; > struct i915_mmu_object; > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 72abc0b..b29d417 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4300,10 +4300,6 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) > I915_WRITE(BCLRPAT(crtc->pipe), 0); > } > > -#define for_each_power_domain(domain, mask) \ > - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > - if ((1 << (domain)) & (mask)) > - > enum intel_display_power_domain > intel_display_port_power_domain(struct intel_encoder *intel_encoder) > { > -- > 1.8.5 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
* [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-11 16:14 ` Daniel Vetter @ 2014-07-12 4:32 ` sagar.a.kamble 2014-07-12 9:50 ` Daniel Vetter 2014-07-23 5:11 ` Daniel Vetter 0 siblings, 2 replies; 7+ messages in thread From: sagar.a.kamble @ 2014-07-12 4:32 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni, Daniel Vetter, Borun Fu, Sagar Kamble From: Borun Fu <borun.fu@intel.com> On VLV, after i915_pm_suspend display power wells are staying power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" Display is staing D0 State. There might be better way/place to power gate these wells. Also, we need to make sure that if wells are power gated due to DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. [Daniel] Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 7 +++---- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++------------- drivers/gpu/drm/i915/intel_drv.h | 1 + 4 files changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 83cb43a..5e4fefd 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -524,12 +524,11 @@ static int i915_drm_freeze(struct drm_device *dev) /* * Disable CRTCs directly since we want to preserve sw state - * for _thaw. + * for _thaw. Also, power gate the CRTC power wells. */ drm_modeset_lock_all(dev); - for_each_crtc(dev, crtc) { - dev_priv->display.crtc_disable(crtc); - } + for_each_crtc(dev, crtc) + intel_crtc_control(crtc, false); drm_modeset_unlock_all(dev); intel_modeset_suspend_hw(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a89c912..54f98d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -179,6 +179,10 @@ enum hpd_pin { list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ if ((intel_connector)->base.encoder == (__encoder)) +#define for_each_power_domain(domain, mask) \ + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ + if ((1 << (domain)) & (mask)) + struct drm_i915_private; struct i915_mmu_object; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fe6f1db..7a1f14f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4300,10 +4300,6 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) I915_WRITE(BCLRPAT(crtc->pipe), 0); } -#define for_each_power_domain(domain, mask) \ - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ - if ((1 << (domain)) & (mask)) - enum intel_display_power_domain intel_display_port_power_domain(struct intel_encoder *intel_encoder) { @@ -4872,21 +4868,14 @@ static void intel_crtc_update_sarea(struct drm_crtc *crtc, } } -/** - * Sets the power management mode of the pipe and plane. - */ -void intel_crtc_update_dpms(struct drm_crtc *crtc) +/* Master function to enable/disable CRTC and corresponding power wells */ +void intel_crtc_control(struct drm_crtc *crtc, bool enable) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_encoder *intel_encoder; enum intel_display_power_domain domain; unsigned long domains; - bool enable = false; - - for_each_encoder_on_crtc(dev, crtc, intel_encoder) - enable |= intel_encoder->connectors_active; if (enable) { if (!intel_crtc->active) { @@ -4907,6 +4896,21 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc) intel_crtc->enabled_power_domains = 0; } } +} + +/** + * Sets the power management mode of the pipe and plane. + */ +void intel_crtc_update_dpms(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct intel_encoder *intel_encoder; + bool enable = false; + + for_each_encoder_on_crtc(dev, crtc, intel_encoder) + enable |= intel_encoder->connectors_active; + + intel_crtc_control(crtc, enable); intel_crtc_update_sarea(crtc, enable); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 016d894..4c24f88 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -755,6 +755,7 @@ void intel_frontbuffer_flip(struct drm_device *dev, void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); void intel_mark_idle(struct drm_device *dev); void intel_crtc_restore_mode(struct drm_crtc *crtc); +void intel_crtc_control(struct drm_crtc *crtc, bool enable); void intel_crtc_update_dpms(struct drm_crtc *crtc); void intel_encoder_destroy(struct drm_encoder *encoder); void intel_connector_dpms(struct drm_connector *, int mode); -- 1.8.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-12 4:32 ` [RFC v2 " sagar.a.kamble @ 2014-07-12 9:50 ` Daniel Vetter 2014-07-23 5:11 ` Daniel Vetter 1 sibling, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2014-07-12 9:50 UTC (permalink / raw) To: sagar.a.kamble; +Cc: Paulo Zanoni, Daniel Vetter, intel-gfx, Borun Fu On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@intel.com wrote: > From: Borun Fu <borun.fu@intel.com> > > On VLV, after i915_pm_suspend display power wells are staying > power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" > Display is staing D0 State. There might be better way/place to power gate > these wells. Also, we need to make sure that if wells are power gated due to > DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. > > v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. > [Daniel] > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> intel_crtc_control looks like a neat idea - I've started also thinking about the enable side and noticed that we'll have similar issues there. But complicated with modeset_global_resources and the differences between the dpms paths and modeset paths. But that's work for another day. Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.c | 7 +++---- > drivers/gpu/drm/i915/i915_drv.h | 4 ++++ > drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++------------- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 4 files changed, 25 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 83cb43a..5e4fefd 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -524,12 +524,11 @@ static int i915_drm_freeze(struct drm_device *dev) > > /* > * Disable CRTCs directly since we want to preserve sw state > - * for _thaw. > + * for _thaw. Also, power gate the CRTC power wells. > */ > drm_modeset_lock_all(dev); > - for_each_crtc(dev, crtc) { > - dev_priv->display.crtc_disable(crtc); > - } > + for_each_crtc(dev, crtc) > + intel_crtc_control(crtc, false); > drm_modeset_unlock_all(dev); > > intel_modeset_suspend_hw(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a89c912..54f98d3 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -179,6 +179,10 @@ enum hpd_pin { > list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ > if ((intel_connector)->base.encoder == (__encoder)) > > +#define for_each_power_domain(domain, mask) \ > + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > + if ((1 << (domain)) & (mask)) > + > struct drm_i915_private; > struct i915_mmu_object; > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index fe6f1db..7a1f14f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4300,10 +4300,6 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) > I915_WRITE(BCLRPAT(crtc->pipe), 0); > } > > -#define for_each_power_domain(domain, mask) \ > - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > - if ((1 << (domain)) & (mask)) > - > enum intel_display_power_domain > intel_display_port_power_domain(struct intel_encoder *intel_encoder) > { > @@ -4872,21 +4868,14 @@ static void intel_crtc_update_sarea(struct drm_crtc *crtc, > } > } > > -/** > - * Sets the power management mode of the pipe and plane. > - */ > -void intel_crtc_update_dpms(struct drm_crtc *crtc) > +/* Master function to enable/disable CRTC and corresponding power wells */ > +void intel_crtc_control(struct drm_crtc *crtc, bool enable) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - struct intel_encoder *intel_encoder; > enum intel_display_power_domain domain; > unsigned long domains; > - bool enable = false; > - > - for_each_encoder_on_crtc(dev, crtc, intel_encoder) > - enable |= intel_encoder->connectors_active; > > if (enable) { > if (!intel_crtc->active) { > @@ -4907,6 +4896,21 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc) > intel_crtc->enabled_power_domains = 0; > } > } > +} > + > +/** > + * Sets the power management mode of the pipe and plane. > + */ > +void intel_crtc_update_dpms(struct drm_crtc *crtc) > +{ > + struct drm_device *dev = crtc->dev; > + struct intel_encoder *intel_encoder; > + bool enable = false; > + > + for_each_encoder_on_crtc(dev, crtc, intel_encoder) > + enable |= intel_encoder->connectors_active; > + > + intel_crtc_control(crtc, enable); > > intel_crtc_update_sarea(crtc, enable); > } > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 016d894..4c24f88 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -755,6 +755,7 @@ void intel_frontbuffer_flip(struct drm_device *dev, > void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); > void intel_mark_idle(struct drm_device *dev); > void intel_crtc_restore_mode(struct drm_crtc *crtc); > +void intel_crtc_control(struct drm_crtc *crtc, bool enable); > void intel_crtc_update_dpms(struct drm_crtc *crtc); > void intel_encoder_destroy(struct drm_encoder *encoder); > void intel_connector_dpms(struct drm_connector *, int mode); > -- > 1.8.5 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-12 4:32 ` [RFC v2 " sagar.a.kamble 2014-07-12 9:50 ` Daniel Vetter @ 2014-07-23 5:11 ` Daniel Vetter 2014-07-25 3:28 ` Dave Airlie 1 sibling, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2014-07-23 5:11 UTC (permalink / raw) To: sagar.a.kamble; +Cc: Paulo Zanoni, Daniel Vetter, intel-gfx, Borun Fu On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@intel.com wrote: > From: Borun Fu <borun.fu@intel.com> > > On VLV, after i915_pm_suspend display power wells are staying > power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" > Display is staing D0 State. There might be better way/place to power gate > these wells. Also, we need to make sure that if wells are power gated due to > DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. > > v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. > [Daniel] > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 s-o-b from the original author (Borun Fu) missing. Added myself since we all work for the same company, but please don't forget this. Every person including the original author, who handles a patch must add their sob line. -Daniel > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 7 +++---- > drivers/gpu/drm/i915/i915_drv.h | 4 ++++ > drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++------------- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 4 files changed, 25 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 83cb43a..5e4fefd 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -524,12 +524,11 @@ static int i915_drm_freeze(struct drm_device *dev) > > /* > * Disable CRTCs directly since we want to preserve sw state > - * for _thaw. > + * for _thaw. Also, power gate the CRTC power wells. > */ > drm_modeset_lock_all(dev); > - for_each_crtc(dev, crtc) { > - dev_priv->display.crtc_disable(crtc); > - } > + for_each_crtc(dev, crtc) > + intel_crtc_control(crtc, false); > drm_modeset_unlock_all(dev); > > intel_modeset_suspend_hw(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a89c912..54f98d3 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -179,6 +179,10 @@ enum hpd_pin { > list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ > if ((intel_connector)->base.encoder == (__encoder)) > > +#define for_each_power_domain(domain, mask) \ > + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > + if ((1 << (domain)) & (mask)) > + > struct drm_i915_private; > struct i915_mmu_object; > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index fe6f1db..7a1f14f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4300,10 +4300,6 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) > I915_WRITE(BCLRPAT(crtc->pipe), 0); > } > > -#define for_each_power_domain(domain, mask) \ > - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > - if ((1 << (domain)) & (mask)) > - > enum intel_display_power_domain > intel_display_port_power_domain(struct intel_encoder *intel_encoder) > { > @@ -4872,21 +4868,14 @@ static void intel_crtc_update_sarea(struct drm_crtc *crtc, > } > } > > -/** > - * Sets the power management mode of the pipe and plane. > - */ > -void intel_crtc_update_dpms(struct drm_crtc *crtc) > +/* Master function to enable/disable CRTC and corresponding power wells */ > +void intel_crtc_control(struct drm_crtc *crtc, bool enable) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - struct intel_encoder *intel_encoder; > enum intel_display_power_domain domain; > unsigned long domains; > - bool enable = false; > - > - for_each_encoder_on_crtc(dev, crtc, intel_encoder) > - enable |= intel_encoder->connectors_active; > > if (enable) { > if (!intel_crtc->active) { > @@ -4907,6 +4896,21 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc) > intel_crtc->enabled_power_domains = 0; > } > } > +} > + > +/** > + * Sets the power management mode of the pipe and plane. > + */ > +void intel_crtc_update_dpms(struct drm_crtc *crtc) > +{ > + struct drm_device *dev = crtc->dev; > + struct intel_encoder *intel_encoder; > + bool enable = false; > + > + for_each_encoder_on_crtc(dev, crtc, intel_encoder) > + enable |= intel_encoder->connectors_active; > + > + intel_crtc_control(crtc, enable); > > intel_crtc_update_sarea(crtc, enable); > } > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 016d894..4c24f88 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -755,6 +755,7 @@ void intel_frontbuffer_flip(struct drm_device *dev, > void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); > void intel_mark_idle(struct drm_device *dev); > void intel_crtc_restore_mode(struct drm_crtc *crtc); > +void intel_crtc_control(struct drm_crtc *crtc, bool enable); > void intel_crtc_update_dpms(struct drm_crtc *crtc); > void intel_encoder_destroy(struct drm_encoder *encoder); > void intel_connector_dpms(struct drm_connector *, int mode); > -- > 1.8.5 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-23 5:11 ` Daniel Vetter @ 2014-07-25 3:28 ` Dave Airlie 2014-07-25 7:26 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: Dave Airlie @ 2014-07-25 3:28 UTC (permalink / raw) To: Daniel Vetter Cc: Borun Fu, Daniel Vetter, intel-gfx@lists.freedesktop.org, Sagar Arun Kamble, Paulo Zanoni On 23 July 2014 15:11, Daniel Vetter <daniel@ffwll.ch> wrote: > On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@intel.com wrote: >> From: Borun Fu <borun.fu@intel.com> >> >> On VLV, after i915_pm_suspend display power wells are staying >> power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" >> Display is staing D0 State. There might be better way/place to power gate >> these wells. Also, we need to make sure that if wells are power gated due to >> DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. >> >> v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. >> [Daniel] >> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> >> Cc: Jani Nikula <jani.nikula@linux.intel.com> >> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > > s-o-b from the original author (Borun Fu) missing. Added myself since we > all work for the same company, but please don't forget this. Every person > including the original author, who handles a patch must add their sob > line. > -Daniel Is this queued or on its way, I was getting a warning on HSW about not entering pc8+ due to display with MST enabled, and I thought it was MSTs fault, but I suspect its just this, mode set turns the global resources power well on, but nothing ever turns it off. Dave. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend 2014-07-25 3:28 ` Dave Airlie @ 2014-07-25 7:26 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2014-07-25 7:26 UTC (permalink / raw) To: Dave Airlie Cc: Paulo Zanoni, Daniel Vetter, intel-gfx@lists.freedesktop.org, Borun Fu, Sagar Arun Kamble On Fri, Jul 25, 2014 at 01:28:48PM +1000, Dave Airlie wrote: > On 23 July 2014 15:11, Daniel Vetter <daniel@ffwll.ch> wrote: > > On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@intel.com wrote: > >> From: Borun Fu <borun.fu@intel.com> > >> > >> On VLV, after i915_pm_suspend display power wells are staying > >> power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" > >> Display is staing D0 State. There might be better way/place to power gate > >> these wells. Also, we need to make sure that if wells are power gated due to > >> DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. > >> > >> v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. > >> [Daniel] > >> > >> Cc: Imre Deak <imre.deak@intel.com> > >> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > >> Cc: Jani Nikula <jani.nikula@linux.intel.com> > >> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > > > > s-o-b from the original author (Borun Fu) missing. Added myself since we > > all work for the same company, but please don't forget this. Every person > > including the original author, who handles a patch must add their sob > > line. > > -Daniel > > Is this queued or on its way, I was getting a warning on HSW about not > entering pc8+ > due to display with MST enabled, and I thought it was MSTs fault, but I suspect > its just this, > > mode set turns the global resources power well on, but nothing ever > turns it off. mst doesn't factor into this. Might need to double-check but from what I've seen mst was only wired into the system s/r paths, not the runtime pm. They're unfortunately not sufficiently shared. So I'd suspect that. The bug here happens when you move/update the cursor (or sprite/primary plane) while the display is off. You'll get unclaimed register read/write errors, no WARNINGs if you hit this one. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-07-25 7:26 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-07-11 15:18 [RFC 1/1] drm/i915: Power gating display wells during i915_pm_suspend sagar.a.kamble 2014-07-11 16:14 ` Daniel Vetter 2014-07-12 4:32 ` [RFC v2 " sagar.a.kamble 2014-07-12 9:50 ` Daniel Vetter 2014-07-23 5:11 ` Daniel Vetter 2014-07-25 3:28 ` Dave Airlie 2014-07-25 7:26 ` Daniel Vetter
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