Re: [PATCH 5/5] drm/i915: BDW can also detect unclaimed registers

[Daniel Vetter <daniel@ffwll.ch>]

On Tue, Jul 15, 2014 at 12:20:01PM -0700, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni <przanoni@gmail.com> wrote:
> 
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > By the time I wrote this patch, it allowed me to catch some problems.
> > But due to patch reordering - in order to prevent fake "regression"
> > reports - this patch may be merged after the fixes of the problems
> > identified by this patch.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Merged all patches except patch 4 (the one that adds the module option).
Thanks.
-Daniel

> > ---
> >  drivers/gpu/drm/i915/i915_drv.c     | 4 ++++
> >  drivers/gpu/drm/i915/intel_uncore.c | 3 +++
> >  2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 8a0cb0c..bdb223c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -303,6 +303,7 @@ static const struct intel_device_info
> > intel_broadwell_d_info = {
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> >         .has_llc = 1,
> >         .has_ddi = 1,
> > +       .has_fpga_dbg = 1,
> >         .has_fbc = 1,
> >         GEN_DEFAULT_PIPEOFFSETS,
> >         IVB_CURSOR_OFFSETS,
> > @@ -314,6 +315,7 @@ static const struct intel_device_info
> > intel_broadwell_m_info = {
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> >         .has_llc = 1,
> >         .has_ddi = 1,
> > +       .has_fpga_dbg = 1,
> >         .has_fbc = 1,
> >         GEN_DEFAULT_PIPEOFFSETS,
> >         IVB_CURSOR_OFFSETS,
> > @@ -325,6 +327,7 @@ static const struct intel_device_info
> > intel_broadwell_gt3d_info = {
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
> > BSD2_RING,
> >         .has_llc = 1,
> >         .has_ddi = 1,
> > +       .has_fpga_dbg = 1,
> >         .has_fbc = 1,
> >         GEN_DEFAULT_PIPEOFFSETS,
> >         IVB_CURSOR_OFFSETS,
> > @@ -336,6 +339,7 @@ static const struct intel_device_info
> > intel_broadwell_gt3m_info = {
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
> > BSD2_RING,
> >         .has_llc = 1,
> >         .has_ddi = 1,
> > +       .has_fpga_dbg = 1,
> >         .has_fbc = 1,
> >         GEN_DEFAULT_PIPEOFFSETS,
> >         IVB_CURSOR_OFFSETS,
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index de5402f..1fcf78b 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -788,6 +788,7 @@ static bool is_gen8_shadowed(struct drm_i915_private
> > *dev_priv, u32 reg)
> >  static void \
> >  gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val,
> > bool trace) { \
> >         REG_WRITE_HEADER; \
> > +       hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> >         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
> >                 if (dev_priv->uncore.forcewake_count == 0) \
> >                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
> > @@ -799,6 +800,8 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
> > reg, u##x val, bool trace
> >         } else { \
> >                 __raw_i915_write##x(dev_priv, reg, val); \
> >         } \
> > +       hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> > +       hsw_unclaimed_reg_detect(dev_priv); \
> >         REG_WRITE_FOOTER; \
> >  }
> >
> > --
> > 2.0.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch