* [PATCH 0/8 v2] Future preparation patches
@ 2014-07-21 9:53 sonika.jindal
2014-07-21 9:53 ` [PATCH 1/8] drm/i915: Adding HAS_GMCH_DISPLAY macro sonika.jindal
` (8 more replies)
0 siblings, 9 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
appropriate check since the code accessed may not have anything to do with
having PCH or not.
v2: Adding new HAS_GMCH_DISPLAY macro suggested by Daniel. Also taking care of
Ironlake(gen 5), by making gen < 5 check suggested by Damien.
Effectively, !HAS_PCH_SPLIT is equivalent to HAS_GMCH_DISPLAY
and HAS_PCH_SPLIT is equivalent to gen >= 5 && !(VALLEYVIEW).
Sonika Jindal (8):
drm/i915: Adding HAS_GMCH_DISPLAY macro
drm/i915: Allowing changing of wm latencies for valid platforms
drm/i915: Returning the right VGA control reg for platforms
drm/i915: Setting legacy palette correctly for different platforms
drm/i915: Returning from increase/decrease of pllclock when invalid
drm/i915: Writing proper check for reading of pipe status reg
drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms
in
drm/i915: Avoid incorrect returning for some platforms
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 8 +++++---
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
4 files changed, 14 insertions(+), 12 deletions(-)
--
1.7.10.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] drm/i915: Adding HAS_GMCH_DISPLAY macro
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 9:53 ` [PATCH 2/8] drm/i915: Allowing changing of wm latencies for valid platforms sonika.jindal
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 991b663..4e28192 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2092,6 +2092,8 @@ struct drm_i915_cmd_table {
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/8] drm/i915: Allowing changing of wm latencies for valid platforms
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
2014-07-21 9:53 ` [PATCH 1/8] drm/i915: Adding HAS_GMCH_DISPLAY macro sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 9:53 ` [PATCH 3/8] drm/i915: Returning the right VGA control reg for platforms sonika.jindal
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fc39610..517c266 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3267,7 +3267,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_device *dev = inode->i_private;
- if (!HAS_PCH_SPLIT(dev))
+ if (HAS_GMCH_DISPLAY(dev))
return -ENODEV;
return single_open(file, pri_wm_latency_show, dev);
@@ -3277,7 +3277,7 @@ static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_device *dev = inode->i_private;
- if (!HAS_PCH_SPLIT(dev))
+ if (HAS_GMCH_DISPLAY(dev))
return -ENODEV;
return single_open(file, spr_wm_latency_show, dev);
@@ -3287,7 +3287,7 @@ static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_device *dev = inode->i_private;
- if (!HAS_PCH_SPLIT(dev))
+ if (HAS_GMCH_DISPLAY(dev))
return -ENODEV;
return single_open(file, cur_wm_latency_show, dev);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] drm/i915: Returning the right VGA control reg for platforms
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
2014-07-21 9:53 ` [PATCH 1/8] drm/i915: Adding HAS_GMCH_DISPLAY macro sonika.jindal
2014-07-21 9:53 ` [PATCH 2/8] drm/i915: Allowing changing of wm latencies for valid platforms sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 9:53 ` [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms sonika.jindal
` (5 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e28192..b932548 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2802,10 +2802,10 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
- if (HAS_PCH_SPLIT(dev))
- return CPU_VGACNTRL;
- else if (IS_VALLEYVIEW(dev))
+ if (IS_VALLEYVIEW(dev))
return VLV_VGACNTRL;
+ else if (INTEL_INFO(dev)->gen >= 5)
+ return CPU_VGACNTRL;
else
return VGACNTRL;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (2 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 3/8] drm/i915: Returning the right VGA control reg for platforms sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 15:49 ` Daniel Vetter
2014-07-21 9:53 ` [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid sonika.jindal
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c89b4ac..442d8ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3847,7 +3847,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
}
/* use legacy palette for Ironlake */
- if (HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
palreg = LGC_PALETTE(pipe);
/* Workaround : Do not read or write the pipe palette/gamma data while
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (3 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 15:50 ` Daniel Vetter
2014-07-21 9:53 ` [PATCH 6/8] drm/i915: Writing proper check for reading of pipe status reg sonika.jindal
` (3 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 442d8ba..f6cf9bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8783,7 +8783,7 @@ static void intel_increase_pllclock(struct drm_device *dev,
int dpll_reg = DPLL(pipe);
int dpll;
- if (HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
return;
if (!dev_priv->lvds_downclock_avail)
@@ -8811,7 +8811,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- if (HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
return;
if (!dev_priv->lvds_downclock_avail)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] drm/i915: Writing proper check for reading of pipe status reg
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (4 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 9:53 ` [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in sonika.jindal
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6cf9bb..f74d1c2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13244,7 +13244,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->pipe[i].source = I915_READ(PIPESRC(i));
- if (!HAS_PCH_SPLIT(dev))
+ if (HAS_GMCH_DISPLAY(dev))
error->pipe[i].stat = I915_READ(PIPESTAT(i));
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (5 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 6/8] drm/i915: Writing proper check for reading of pipe status reg sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 15:51 ` Daniel Vetter
2014-07-21 9:53 ` [PATCH 8/8] drm/i915: Avoid incorrect returning for some platforms sonika.jindal
2014-07-21 15:52 ` [PATCH 0/8 v2] Future preparation patches Daniel Vetter
8 siblings, 1 reply; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f8f4ca..458dd4f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1562,7 +1562,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (IS_VALLEYVIEW(dev)) {
intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes;
- } else if (!HAS_PCH_SPLIT(dev)) {
+ } else if (INTEL_INFO(dev)->gen < 5) {
intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes;
} else if (HAS_DDI(dev)) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] drm/i915: Avoid incorrect returning for some platforms
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (6 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in sonika.jindal
@ 2014-07-21 9:53 ` sonika.jindal
2014-07-21 15:52 ` [PATCH 0/8 v2] Future preparation patches Daniel Vetter
8 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-21 9:53 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 458dd4f..ecdb2d5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -882,7 +882,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
struct intel_encoder *encoder;
int count = 0, count_hdmi = 0;
- if (!HAS_PCH_SPLIT(dev))
+ if (HAS_GMCH_DISPLAY(dev))
return false;
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms
2014-07-21 9:53 ` [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms sonika.jindal
@ 2014-07-21 15:49 ` Daniel Vetter
2014-07-22 5:48 ` [PATCH v2] " sonika.jindal
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2014-07-21 15:49 UTC (permalink / raw)
To: sonika.jindal; +Cc: intel-gfx
On Mon, Jul 21, 2014 at 03:23:41PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c89b4ac..442d8ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3847,7 +3847,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> }
>
> /* use legacy palette for Ironlake */
> - if (HAS_PCH_SPLIT(dev))
> + if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
Imo we should check for !HAS_GMCH_DISPLAY here.
-Daniel
> palreg = LGC_PALETTE(pipe);
>
> /* Workaround : Do not read or write the pipe palette/gamma data while
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid
2014-07-21 9:53 ` [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid sonika.jindal
@ 2014-07-21 15:50 ` Daniel Vetter
2014-07-22 5:46 ` [PATCH v2] " sonika.jindal
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2014-07-21 15:50 UTC (permalink / raw)
To: sonika.jindal; +Cc: intel-gfx
On Mon, Jul 21, 2014 at 03:23:42PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 442d8ba..f6cf9bb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8783,7 +8783,7 @@ static void intel_increase_pllclock(struct drm_device *dev,
> int dpll_reg = DPLL(pipe);
> int dpll;
>
> - if (HAS_PCH_SPLIT(dev))
> + if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
Same as with the previous patch.
-Daniel
> return;
>
> if (!dev_priv->lvds_downclock_avail)
> @@ -8811,7 +8811,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev))
> return;
>
> if (!dev_priv->lvds_downclock_avail)
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in
2014-07-21 9:53 ` [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in sonika.jindal
@ 2014-07-21 15:51 ` Daniel Vetter
2014-07-22 5:43 ` [PATCH v2] " sonika.jindal
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2014-07-21 15:51 UTC (permalink / raw)
To: sonika.jindal; +Cc: intel-gfx
On Mon, Jul 21, 2014 at 03:23:44PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 5f8f4ca..458dd4f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1562,7 +1562,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> if (IS_VALLEYVIEW(dev)) {
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> - } else if (!HAS_PCH_SPLIT(dev)) {
> + } else if (INTEL_INFO(dev)->gen < 5) {
Maybe make this explicit and check for IS_G4X(dev) instead? It's the only
platform where this case applies, and also nicely highlights how the g4x_
prefix of the functions matches.
-Daniel
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> } else if (HAS_DDI(dev)) {
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/8 v2] Future preparation patches
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
` (7 preceding siblings ...)
2014-07-21 9:53 ` [PATCH 8/8] drm/i915: Avoid incorrect returning for some platforms sonika.jindal
@ 2014-07-21 15:52 ` Daniel Vetter
8 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2014-07-21 15:52 UTC (permalink / raw)
To: sonika.jindal; +Cc: intel-gfx
On Mon, Jul 21, 2014 at 03:23:37PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
> appropriate check since the code accessed may not have anything to do with
> having PCH or not.
>
> v2: Adding new HAS_GMCH_DISPLAY macro suggested by Daniel. Also taking care of
> Ironlake(gen 5), by making gen < 5 check suggested by Damien.
> Effectively, !HAS_PCH_SPLIT is equivalent to HAS_GMCH_DISPLAY
> and HAS_PCH_SPLIT is equivalent to gen >= 5 && !(VALLEYVIEW).
>
> Sonika Jindal (8):
> drm/i915: Adding HAS_GMCH_DISPLAY macro
> drm/i915: Allowing changing of wm latencies for valid platforms
> drm/i915: Returning the right VGA control reg for platforms
> drm/i915: Setting legacy palette correctly for different platforms
> drm/i915: Returning from increase/decrease of pllclock when invalid
> drm/i915: Writing proper check for reading of pipe status reg
> drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms
> in
> drm/i915: Avoid incorrect returning for some platforms
I commented on a few patches, all others merged to dinq.
Thanks, Daniel
>
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
> drivers/gpu/drm/i915/i915_drv.h | 8 +++++---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
> 4 files changed, 14 insertions(+), 12 deletions(-)
>
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in
2014-07-21 15:51 ` Daniel Vetter
@ 2014-07-22 5:43 ` sonika.jindal
2014-07-22 7:13 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: sonika.jindal @ 2014-07-22 5:43 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
v2: Adding IS_G4X instead of gen < 5 as suggested by Daniel
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f8f4ca..2d1a3cb 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1562,7 +1562,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (IS_VALLEYVIEW(dev)) {
intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes;
- } else if (!HAS_PCH_SPLIT(dev)) {
+ } else if (IS_G4X(dev)) {
intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes;
} else if (HAS_DDI(dev)) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915: Returning from increase/decrease of pllclock when invalid
2014-07-21 15:50 ` Daniel Vetter
@ 2014-07-22 5:46 ` sonika.jindal
0 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-22 5:46 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
v2: Adding !HAS_GMCH_DISPLAY(dev)
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e73798..bd14600 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8783,7 +8783,7 @@ static void intel_increase_pllclock(struct drm_device *dev,
int dpll_reg = DPLL(pipe);
int dpll;
- if (HAS_PCH_SPLIT(dev))
+ if (!HAS_GMCH_DISPLAY(dev))
return;
if (!dev_priv->lvds_downclock_avail)
@@ -8811,7 +8811,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- if (HAS_PCH_SPLIT(dev))
+ if (!HAS_GMCH_DISPLAY(dev))
return;
if (!dev_priv->lvds_downclock_avail)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915: Setting legacy palette correctly for different platforms
2014-07-21 15:49 ` Daniel Vetter
@ 2014-07-22 5:48 ` sonika.jindal
0 siblings, 0 replies; 17+ messages in thread
From: sonika.jindal @ 2014-07-22 5:48 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
v2: Adding !HAS_GMCH_DISPLAY(dev)
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c89b4ac..3e73798 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3847,7 +3847,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
}
/* use legacy palette for Ironlake */
- if (HAS_PCH_SPLIT(dev))
+ if (!HAS_GMCH_DISPLAY(dev))
palreg = LGC_PALETTE(pipe);
/* Workaround : Do not read or write the pipe palette/gamma data while
--
1.7.10.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in
2014-07-22 5:43 ` [PATCH v2] " sonika.jindal
@ 2014-07-22 7:13 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2014-07-22 7:13 UTC (permalink / raw)
To: sonika.jindal; +Cc: intel-gfx
On Tue, Jul 22, 2014 at 11:13:46AM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> v2: Adding IS_G4X instead of gen < 5 as suggested by Daniel
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Merged the remaining patches, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 5f8f4ca..2d1a3cb 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1562,7 +1562,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> if (IS_VALLEYVIEW(dev)) {
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> - } else if (!HAS_PCH_SPLIT(dev)) {
> + } else if (IS_G4X(dev)) {
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> } else if (HAS_DDI(dev)) {
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2014-07-22 7:13 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-07-21 9:53 [PATCH 0/8 v2] Future preparation patches sonika.jindal
2014-07-21 9:53 ` [PATCH 1/8] drm/i915: Adding HAS_GMCH_DISPLAY macro sonika.jindal
2014-07-21 9:53 ` [PATCH 2/8] drm/i915: Allowing changing of wm latencies for valid platforms sonika.jindal
2014-07-21 9:53 ` [PATCH 3/8] drm/i915: Returning the right VGA control reg for platforms sonika.jindal
2014-07-21 9:53 ` [PATCH 4/8] drm/i915: Setting legacy palette correctly for different platforms sonika.jindal
2014-07-21 15:49 ` Daniel Vetter
2014-07-22 5:48 ` [PATCH v2] " sonika.jindal
2014-07-21 9:53 ` [PATCH 5/8] drm/i915: Returning from increase/decrease of pllclock when invalid sonika.jindal
2014-07-21 15:50 ` Daniel Vetter
2014-07-22 5:46 ` [PATCH v2] " sonika.jindal
2014-07-21 9:53 ` [PATCH 6/8] drm/i915: Writing proper check for reading of pipe status reg sonika.jindal
2014-07-21 9:53 ` [PATCH 7/8] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in sonika.jindal
2014-07-21 15:51 ` Daniel Vetter
2014-07-22 5:43 ` [PATCH v2] " sonika.jindal
2014-07-22 7:13 ` Daniel Vetter
2014-07-21 9:53 ` [PATCH 8/8] drm/i915: Avoid incorrect returning for some platforms sonika.jindal
2014-07-21 15:52 ` [PATCH 0/8 v2] Future preparation patches Daniel Vetter
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