From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend Date: Fri, 25 Jul 2014 09:26:27 +0200 Message-ID: <20140725072627.GG4747@phenom.ffwll.local> References: <20140711161407.GG17271@phenom.ffwll.local> <1405139547-13043-1-git-send-email-sagar.a.kamble@intel.com> <20140723051118.GQ15237@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by gabe.freedesktop.org (Postfix) with ESMTP id 780B66E7E2 for ; Fri, 25 Jul 2014 00:26:18 -0700 (PDT) Received: by mail-wi0-f181.google.com with SMTP id bs8so467281wib.14 for ; Fri, 25 Jul 2014 00:26:17 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Dave Airlie Cc: Paulo Zanoni , Daniel Vetter , "intel-gfx@lists.freedesktop.org" , Borun Fu , Sagar Arun Kamble List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 25, 2014 at 01:28:48PM +1000, Dave Airlie wrote: > On 23 July 2014 15:11, Daniel Vetter wrote: > > On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@intel.com wrote: > >> From: Borun Fu > >> > >> On VLV, after i915_pm_suspend display power wells are staying > >> power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" > >> Display is staing D0 State. There might be better way/place to power gate > >> these wells. Also, we need to make sure that if wells are power gated due to > >> DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. > >> > >> v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. > >> [Daniel] > >> > >> Cc: Imre Deak > >> Cc: Paulo Zanoni > >> Cc: Daniel Vetter > >> Cc: Jani Nikula > >> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > > > > s-o-b from the original author (Borun Fu) missing. Added myself since we > > all work for the same company, but please don't forget this. Every person > > including the original author, who handles a patch must add their sob > > line. > > -Daniel > > Is this queued or on its way, I was getting a warning on HSW about not > entering pc8+ > due to display with MST enabled, and I thought it was MSTs fault, but I suspect > its just this, > > mode set turns the global resources power well on, but nothing ever > turns it off. mst doesn't factor into this. Might need to double-check but from what I've seen mst was only wired into the system s/r paths, not the runtime pm. They're unfortunately not sufficiently shared. So I'd suspect that. The bug here happens when you move/update the cursor (or sprite/primary plane) while the display is off. You'll get unclaimed register read/write errors, no WARNINGs if you hit this one. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch