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* [PATCH] drm/i915: Introduce FBC False Color for debug purposes.
@ 2014-06-20 13:46 Rodrigo Vivi
  2014-07-07 14:59 ` Daniel Vetter
  0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2014-06-20 13:46 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

With this bit enabled, HW changes the color when compressing frames for
debug purposes.

ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 70 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/i915_reg.h     |  1 +
 drivers/gpu/drm/i915/intel_pm.c     |  6 ++++
 4 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6b7b32b..c2019a6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1508,6 +1508,75 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_fbc_fc_show(struct seq_file *m, void *data)
+{
+	struct drm_device *dev = m->private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	drm_modeset_lock_all(dev);
+	seq_printf(m, "False Color: %s\n", yesno(dev_priv->fbc.false_color));
+	drm_modeset_unlock_all(dev);
+
+	return 0;
+}
+
+static int i915_fbc_fc_open(struct inode *inode, struct file *file)
+{
+	struct drm_device *dev = inode->i_private;
+
+	if (INTEL_INFO(dev)->gen < 5)
+		return -ENODEV;
+
+	return single_open(file, i915_fbc_fc_show, dev);
+}
+
+static ssize_t i915_fbc_fc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct drm_device *dev = m->private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret;
+	char tmp[2];
+	int false_color;
+	u32 val;
+
+	if (len > 2)
+		return -EINVAL;
+
+	if (copy_from_user(tmp, ubuf, len))
+		return -EFAULT;
+
+	tmp[1] = '\0';
+
+	ret = sscanf(tmp, "%d", &false_color);
+	if (ret != 1)
+		return -EINVAL;
+
+	drm_modeset_lock_all(dev);
+
+	val = I915_READ(ILK_DPFC_CONTROL);
+	dev_priv->fbc.false_color = false_color;
+
+	I915_WRITE(ILK_DPFC_CONTROL, false_color ?
+		   (val | FBC_CTL_FALSE_COLOR) :
+		   (val & ~FBC_CTL_FALSE_COLOR));
+
+	drm_modeset_unlock_all(dev);
+
+	return len;
+}
+
+static const struct file_operations i915_fbc_fops = {
+	.release = single_release,
+	.owner = THIS_MODULE,
+	.read = seq_read,
+	.open = i915_fbc_fc_open,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_fbc_fc_write,
+};
+
 static int i915_ips_status(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -3858,6 +3927,7 @@ static const struct i915_debugfs_files {
 	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
 	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
 	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
+	{"i915_fbc_false_color", &i915_fbc_fops},
 };
 
 void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..ec24b15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -607,6 +607,8 @@ struct i915_fbc {
 	struct drm_mm_node *compressed_fb;
 	struct drm_mm_node *compressed_llb;
 
+	bool false_color;
+
 	struct intel_fbc_work {
 		struct delayed_work work;
 		struct drm_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3488567..c70df22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1495,6 +1495,7 @@ enum punit_power_well {
 /* Framebuffer compression for Ironlake */
 #define ILK_DPFC_CB_BASE	0x43200
 #define ILK_DPFC_CONTROL	0x43208
+#define   FBC_CTL_FALSE_COLOR	(1<<10)
 /* The bit 28-8 is reserved */
 #define   DPFC_RESERVED		(0x1FFFFF00)
 #define ILK_DPFC_RECOMP_CTL	0x4320c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d771e82..216cb19 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -236,6 +236,9 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc)
 	if (IS_GEN5(dev))
 		dpfc_ctl |= obj->fence_reg;
 
+	if (dev_priv->fbc.false_color)
+		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
 	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 	/* enable it... */
@@ -290,6 +293,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 	dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 
+	if (dev_priv->fbc.false_color)
+		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 
 	if (IS_IVYBRIDGE(dev)) {
-- 
1.9.0

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915: Introduce FBC False Color for debug purposes.
@ 2014-07-31  4:01 Ben Widawsky
  2014-07-31 19:07 ` [PATCH] " Rodrigo Vivi
  0 siblings, 1 reply; 8+ messages in thread
From: Ben Widawsky @ 2014-07-31  4:01 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: Daniel Vetter, intel-gfx

On Wed, Jul 30, 2014 at 09:26:17AM -0700, Rodrigo Vivi wrote:
> With this bit enabled, HW changes the color when compressing frames for
> debug purposes.
> 
> ALthough the simple way to enable a single bit is over intel_reg_write,
> this value is overwriten on next update_fbc so depending on the workload
> it is not possible to set this bit with intel-gpu-tools. So this patch
> introduces a persistent way to enable false color over debugfs.
> 
> v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
> v3: (Ville) only do false color for IVB+ since according to spec bit is
>     MBZ before IVB.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I don't quite understand the motivation for a get() other than debugging
the interface itself (if your set is broken). If anything, get should
read back the register in case you're trying to debug funky colors, but
I am not strongly opinionated here.

Just to make sure, false color works on VLV/CHV  (for the gen check)?

With the above address:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 42 +++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h     |  2 ++
>  drivers/gpu/drm/i915/i915_reg.h     |  1 +
>  drivers/gpu/drm/i915/intel_pm.c     |  3 +++
>  4 files changed, 48 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9e737b7..bcfdc00 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_fbc_fc_get(void *data, u64 *val)
> +{
> +	struct drm_device *dev = data;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	if (INTEL_INFO(dev)->gen < 7)
> +		return -ENODEV;
> +
> +	drm_modeset_lock_all(dev);
> +	*val = dev_priv->fbc.false_color;
> +	drm_modeset_unlock_all(dev);
> +
> +	return 0;
> +}
> +
> +static int i915_fbc_fc_set(void *data, u64 val)
> +{
> +	struct drm_device *dev = data;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 reg;
> +
> +	if (INTEL_INFO(dev)->gen < 7)
> +		return -ENODEV;
> +
> +	drm_modeset_lock_all(dev);
> +
> +	reg = I915_READ(ILK_DPFC_CONTROL);
> +	dev_priv->fbc.false_color = val;
> +
> +	I915_WRITE(ILK_DPFC_CONTROL, val ?
> +		   (reg | FBC_CTL_FALSE_COLOR) :
> +		   (reg & ~FBC_CTL_FALSE_COLOR));
> +
> +	drm_modeset_unlock_all(dev);
> +	return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
> +			i915_fbc_fc_get, i915_fbc_fc_set,
> +			"%llu\n");
> +
>  static int i915_ips_status(struct seq_file *m, void *unused)
>  {
>  	struct drm_info_node *node = m->private;
> @@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files {
>  	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
>  	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
>  	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
> +	{"i915_fbc_false_color", &i915_fbc_fc_fops},
>  };
>  
>  void intel_display_crc_init(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18c9ad8..3018bf5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -636,6 +636,8 @@ struct i915_fbc {
>  	struct drm_mm_node compressed_fb;
>  	struct drm_mm_node *compressed_llb;
>  
> +	bool false_color;
> +
>  	struct intel_fbc_work {
>  		struct delayed_work work;
>  		struct drm_crtc *crtc;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 28e21ed..b5d295a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1540,6 +1540,7 @@ enum punit_power_well {
>  /* Framebuffer compression for Ironlake */
>  #define ILK_DPFC_CB_BASE	0x43200
>  #define ILK_DPFC_CONTROL	0x43208
> +#define   FBC_CTL_FALSE_COLOR	(1<<10)
>  /* The bit 28-8 is reserved */
>  #define   DPFC_RESERVED		(0x1FFFFF00)
>  #define ILK_DPFC_RECOMP_CTL	0x4320c
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1ddd4df..338a80b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
>  
>  	dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
>  
> +	if (dev_priv->fbc.false_color)
> +		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
> +
>  	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>  
>  	if (IS_IVYBRIDGE(dev)) {
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2014-08-04  8:14 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-06-20 13:46 [PATCH] drm/i915: Introduce FBC False Color for debug purposes Rodrigo Vivi
2014-07-07 14:59 ` Daniel Vetter
2014-07-07 18:42   ` Rodrigo Vivi
2014-07-28 13:04     ` Ville Syrjälä
  -- strict thread matches above, loose matches on Subject: below --
2014-07-31  4:01 [PATCH 1/2] " Ben Widawsky
2014-07-31 19:07 ` [PATCH] " Rodrigo Vivi
2014-08-01 10:27   ` Ville Syrjälä
2014-08-01  9:04     ` Rodrigo Vivi
2014-08-04  8:14       ` Daniel Vetter

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