From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values Date: Mon, 28 Jul 2014 18:17:35 +0300 Message-ID: <20140728151735.GI27580@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-4-git-send-email-ville.syrjala@linux.intel.com> <53C13C27.5090306@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FE3D6E10F for ; Mon, 28 Jul 2014 08:18:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <53C13C27.5090306@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Deepak S Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, Jul 12, 2014 at 07:16:15PM +0530, Deepak S wrote: > = > On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > CHV wants even rps opcodes so make sure the min/max/rpe values are also > > even. > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++++++ > > drivers/gpu/drm/i915/intel_pm.c | 19 ++++++++++++++----- > > 2 files changed, 22 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915= /i915_debugfs.c > > index 415010e..9b01e7c 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -3566,6 +3566,10 @@ i915_max_freq_set(void *data, u64 val) > > if (IS_VALLEYVIEW(dev)) { > > val =3D vlv_freq_opcode(dev_priv, val); > > = > > + /* CHV needs even encode values */ > > + if (IS_CHERRYVIEW(dev)) > > + val &=3D ~1; > > + > > hw_max =3D dev_priv->rps.max_freq; > > hw_min =3D dev_priv->rps.min_freq; > > } else { > > @@ -3647,6 +3651,10 @@ i915_min_freq_set(void *data, u64 val) > > if (IS_VALLEYVIEW(dev)) { > > val =3D vlv_freq_opcode(dev_priv, val); > > = > > + /* CHV needs even encode values */ > > + if (IS_CHERRYVIEW(dev)) > > + val =3D ALIGN(val, 2); > > + > > hw_max =3D dev_priv->rps.max_freq; > > hw_min =3D dev_priv->rps.min_freq; > > } else { > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 10c9c02..e3f23c2 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3924,21 +3924,30 @@ static void cherryview_init_gt_powersave(struct= drm_device *dev) > > mutex_lock(&dev_priv->rps.hw_lock); > > = > > dev_priv->rps.max_freq =3D cherryview_rps_max_freq(dev_priv); > > + if (WARN_ON_ONCE(dev_priv->rps.max_freq & 1)) > > + dev_priv->rps.max_freq &=3D ~1; > = > Cannot we use ALIGN Here? The idea was to round max freq down and min freq up. > = > Other than this it looks fine > = > Reviewed-by: Deepak S > = > = > > dev_priv->rps.rp0_freq =3D dev_priv->rps.max_freq; > > DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", > > vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), > > dev_priv->rps.max_freq); > > = > > - dev_priv->rps.efficient_freq =3D cherryview_rps_rpe_freq(dev_priv); > > - DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", > > - vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), > > - dev_priv->rps.efficient_freq); > > - > > dev_priv->rps.min_freq =3D cherryview_rps_min_freq(dev_priv); > > + if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1)) > > + dev_priv->rps.min_freq =3D ALIGN(dev_priv->rps.min_freq, 2); > > DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", > > vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), > > dev_priv->rps.min_freq); > > = > > + dev_priv->rps.efficient_freq =3D cherryview_rps_rpe_freq(dev_priv); > > + if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1)) > > + dev_priv->rps.efficient_freq &=3D ~1; > > + dev_priv->rps.efficient_freq =3D clamp(dev_priv->rps.efficient_freq, > > + dev_priv->rps.min_freq, > > + dev_priv->rps.max_freq); > > + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", > > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), > > + dev_priv->rps.efficient_freq); > > + > > /* Preserve min/max settings in case of re-init */ > > if (dev_priv->rps.max_freq_softlimit =3D=3D 0) > > dev_priv->rps.max_freq_softlimit =3D dev_priv->rps.max_freq; -- = Ville Syrj=E4l=E4 Intel OTC