From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 17/40] drm/i915: Add chv cmnlane power wells Date: Mon, 28 Jul 2014 18:18:40 +0300 Message-ID: <20140728151840.GJ27580@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-18-git-send-email-ville.syrjala@linux.intel.com> <1406289300.23035.4.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 674C86E363 for ; Mon, 28 Jul 2014 08:18:47 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406289300.23035.4.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 25, 2014 at 02:55:00PM +0300, Imre Deak wrote: > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > = > > CHV has two display PHYs so there are also two cmnlane power wells. Add > > the approriate code to power the wells up/down. > > = > > Like on VLV we do the cmnreset assert/deassert and the DPLL refclock > > enabling at approriate times. > > = > > This code actually works on my bsw. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++++++++++++++++++= ++++++++ > > 2 files changed, 90 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index d246609..19e68d6 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -512,6 +512,7 @@ enum punit_power_well { > > PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 =3D 9, > > PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > > PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > > + PUNIT_POWER_WELL_DPIO_CMN_D =3D 12, > > = > > PUNIT_POWER_WELL_NUM, > > }; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index e2b956e..f88490b 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(stru= ct drm_i915_private *dev_priv, > > vlv_set_power_well(dev_priv, power_well, false); > > } > > = > > +static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *de= v_priv, > > + struct i915_power_well *power_well) > > +{ > > + enum dpio_phy phy; > > + > > + WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC && > > + power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D); > > + > > + /* > > + * Enable the CRI clock source so we can get at the > > + * display and the reference clock for VGA > > + * hotplug / manual detection. > > + */ > > + if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) { > > + phy =3D DPIO_PHY0; > > + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > > + DPLL_REFA_CLK_ENABLE_VLV); > > + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > > + DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > = > Any reason the two clocks are enabled sequentially? For PHY1 you don't > do this.. I think I meant to enable the ref clock for both pipes A and B. So the first rmw should have hit DPLL(PIPE_A). > In any case: > Reviewed-by: Imre Deak > = > > + } else { > > + phy =3D DPIO_PHY1; > > + I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | > > + DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > > + } > > + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ > > + vlv_set_power_well(dev_priv, power_well, true); > > + > > + /* Poll for phypwrgood signal */ > > + if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) > > + DRM_ERROR("Display PHY %d is not power up\n", phy); > > + > > + I915_WRITE(DISPLAY_PHY_CONTROL, > > + PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL))); > > +} > > + > > +static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *d= ev_priv, > > + struct i915_power_well *power_well) > > +{ > > + enum dpio_phy phy; > > + > > + WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC && > > + power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D); > > + > > + if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) { > > + phy =3D DPIO_PHY0; > > + assert_pll_disabled(dev_priv, PIPE_A); > > + assert_pll_disabled(dev_priv, PIPE_B); > > + } else { > > + phy =3D DPIO_PHY1; > > + assert_pll_disabled(dev_priv, PIPE_C); > > + } > > + > > + I915_WRITE(DISPLAY_PHY_CONTROL, > > + PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL))); > > + > > + vlv_set_power_well(dev_priv, power_well, false); > > +} > > + > > static void check_power_well_state(struct drm_i915_private *dev_priv, > > struct i915_power_well *power_well) > > { > > @@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > > BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > > BIT(POWER_DOMAIN_INIT)) > > = > > +#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ > > + BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > > + BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > > + BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ > > + BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > > + BIT(POWER_DOMAIN_INIT)) > > + > > +#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ > > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > + BIT(POWER_DOMAIN_INIT)) > > + > > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = =3D { > > .sync_hw =3D i9xx_always_on_power_well_noop, > > .enable =3D i9xx_always_on_power_well_noop, > > @@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = =3D { > > }, > > }; > > = > > +static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = =3D { > > + .sync_hw =3D vlv_power_well_sync_hw, > > + .enable =3D chv_dpio_cmn_power_well_enable, > > + .disable =3D chv_dpio_cmn_power_well_disable, > > + .is_enabled =3D vlv_power_well_enabled, > > +}; > > + > > static struct i915_power_well chv_power_wells[] =3D { > > { > > .name =3D "always-on", > > @@ -6505,6 +6582,18 @@ static struct i915_power_well chv_power_wells[] = =3D { > > .domains =3D VLV_ALWAYS_ON_POWER_DOMAINS, > > .ops =3D &i9xx_always_on_power_well_ops, > > }, > > + { > > + .name =3D "dpio-common-bc", > > + .domains =3D CHV_DPIO_CMN_BC_POWER_DOMAINS, > > + .data =3D PUNIT_POWER_WELL_DPIO_CMN_BC, > > + .ops =3D &chv_dpio_cmn_power_well_ops, > > + }, > > + { > > + .name =3D "dpio-common-d", > > + .domains =3D CHV_DPIO_CMN_D_POWER_DOMAINS, > > + .data =3D PUNIT_POWER_WELL_DPIO_CMN_D, > > + .ops =3D &chv_dpio_cmn_power_well_ops, > > + }, > > }; > > = > > static struct i915_power_well *lookup_power_well(struct drm_i915_priva= te *dev_priv, > = -- = Ville Syrj=E4l=E4 Intel OTC