From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 22/40] drm/i915: Add chv port D TX wells Date: Mon, 28 Jul 2014 18:19:19 +0300 Message-ID: <20140728151919.GK27580@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-23-git-send-email-ville.syrjala@linux.intel.com> <1406295029.23035.12.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CE906E393 for ; Mon, 28 Jul 2014 08:19:23 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406295029.23035.12.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote: > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > = > > Add the TX wells for port D. The Punit subsystem numbers are a total > > guess at this time. Also I'm not sure these even exist. Certainly the > > Punit in current hardware doesn't deal with these. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ > > 2 files changed, 27 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 3d1fef4..191df9e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -525,6 +525,10 @@ enum punit_power_well { > > PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > > PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > > PUNIT_POWER_WELL_DPIO_CMN_D =3D 12, > > + /* FIXME: guesswork below */ > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 =3D 13, > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 =3D 14, > > + PUNIT_POWER_WELL_DPIO_RX2 =3D 15, > > = > > PUNIT_POWER_WELL_NUM, > > }; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index cae936c..55f3e6b 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > > BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > BIT(POWER_DOMAIN_INIT)) > > = > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ > > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > + BIT(POWER_DOMAIN_INIT)) > > + > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > = > Atm, for all other ports we power up all lanes regardless of the actual > configuration (until the PHY side setup is proved to work fine). So for > consistency I'd do the same here too. With that change: We do that here too. '.domains =3D 01 | 23' for both tx-d wells. Or am I missing something? > = > Reviewed-by: Imre Deak > = > > + BIT(POWER_DOMAIN_INIT)) > > + > > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = =3D { > > .sync_hw =3D i9xx_always_on_power_well_noop, > > .enable =3D i9xx_always_on_power_well_noop, > > @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = =3D { > > .ops =3D &vlv_dpio_power_well_ops, > > .data =3D PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > > }, > > + { > > + .name =3D "dpio-tx-d-01", > > + .domains =3D CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > + CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > + .ops =3D &vlv_dpio_power_well_ops, > > + .data =3D PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, > > + }, > > + { > > + .name =3D "dpio-tx-d-23", > > + .domains =3D CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > + CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > + .ops =3D &vlv_dpio_power_well_ops, > > + .data =3D PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, > > + }, > > #endif > > }; > > = > = -- = Ville Syrj=E4l=E4 Intel OTC