From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH] drm/i915: Fix read back of plane stride
	register
Date: Tue, 29 Jul 2014 12:46:14 +0300
Message-ID: <20140729094614.GQ27580@intel.com>
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On Mon, Jul 28, 2014 at 07:56:27PM +0100, rafael.barbalho@intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
> =

> According to the specifications bit 6 is actually valid in the stride reg=
ister.
> =

> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Cc: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>

Indeed, min stride alignment is 64 bytes so we want bit 6 as well.

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/=
intel_display.c
> index 99eb7ca..52dab31 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6221,7 +6221,7 @@ static void i9xx_get_plane_config(struct intel_crtc=
 *crtc,
>  	crtc->base.primary->fb->height =3D ((val >> 0) & 0xfff) + 1;
>  =

>  	val =3D I915_READ(DSPSTRIDE(pipe));
> -	crtc->base.primary->fb->pitches[0] =3D val & 0xffffff80;
> +	crtc->base.primary->fb->pitches[0] =3D val & 0xffffffc0;
>  =

>  	aligned_height =3D intel_align_height(dev, crtc->base.primary->fb->heig=
ht,
>  					    plane_config->tiled);
> @@ -7241,7 +7241,7 @@ static void ironlake_get_plane_config(struct intel_=
crtc *crtc,
>  	crtc->base.primary->fb->height =3D ((val >> 0) & 0xfff) + 1;
>  =

>  	val =3D I915_READ(DSPSTRIDE(pipe));
> -	crtc->base.primary->fb->pitches[0] =3D val & 0xffffff80;
> +	crtc->base.primary->fb->pitches[0] =3D val & 0xffffffc0;
>  =

>  	aligned_height =3D intel_align_height(dev, crtc->base.primary->fb->heig=
ht,
>  					    plane_config->tiled);
> -- =

> 2.0.3

-- =

Ville Syrj=E4l=E4
Intel OTC