From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper. Date: Tue, 29 Jul 2014 09:59:53 -0700 Message-ID: <20140729095953.7b25ed1d@jbarnes-desktop> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-30-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pd0-f173.google.com (mail-pd0-f173.google.com [209.85.192.173]) by gabe.freedesktop.org (Postfix) with ESMTP id 552E96E48A for ; Tue, 29 Jul 2014 09:59:47 -0700 (PDT) Received: by mail-pd0-f173.google.com with SMTP id w10so11825483pde.4 for ; Tue, 29 Jul 2014 09:59:47 -0700 (PDT) In-Reply-To: <1403910271-24984-30-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 28 Jun 2014 02:04:20 +0300 ville.syrjala@linux.intel.com wrote: > From: Kenneth Graunke > > We'll want to reuse this for a workaround. > > Signed-off-by: Kenneth Graunke > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 36 ++++++++++++++++++++------------- > 1 file changed, 22 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2faef26..97796b1 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, > } > > static int > +gen8_emit_pipe_control(struct intel_engine_cs *ring, > + u32 flags, u32 scratch_addr) > +{ > + int ret; > + > + ret = intel_ring_begin(ring, 6); > + if (ret) > + return ret; > + > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); > + intel_ring_emit(ring, flags); > + intel_ring_emit(ring, scratch_addr); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, 0); > + intel_ring_advance(ring); > + > + return 0; > +} > + > +static int > gen8_render_ring_flush(struct intel_engine_cs *ring, > u32 invalidate_domains, u32 flush_domains) > { > @@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, > flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; > } > > - ret = intel_ring_begin(ring, 6); > - if (ret) > - return ret; > - > - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); > - intel_ring_emit(ring, flags); > - intel_ring_emit(ring, scratch_addr); > - intel_ring_emit(ring, 0); > - intel_ring_emit(ring, 0); > - intel_ring_emit(ring, 0); > - intel_ring_advance(ring); > - > - return 0; > - > + return gen8_emit_pipe_control(ring, flags, scratch_addr); > } > > static void ring_write_tail(struct intel_engine_cs *ring, Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center