From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 22/40] drm/i915: Add chv port D TX wells Date: Tue, 29 Jul 2014 12:27:28 +0200 Message-ID: <20140729102728.GL4747@phenom.ffwll.local> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-23-git-send-email-ville.syrjala@linux.intel.com> <1406295029.23035.12.camel@intelbox> <20140728151919.GK27580@intel.com> <1406627676.9702.15.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f179.google.com (mail-we0-f179.google.com [74.125.82.179]) by gabe.freedesktop.org (Postfix) with ESMTP id BB8066E20D for ; Tue, 29 Jul 2014 03:27:22 -0700 (PDT) Received: by mail-we0-f179.google.com with SMTP id u57so8715138wes.38 for ; Tue, 29 Jul 2014 03:27:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406627676.9702.15.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 12:54:36PM +0300, Imre Deak wrote: > On Mon, 2014-07-28 at 18:19 +0300, Ville Syrj=E4l=E4 wrote: > > On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote: > > > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrot= e: > > > > From: Ville Syrj=E4l=E4 > > > > = > > > > Add the TX wells for port D. The Punit subsystem numbers are a total > > > > guess at this time. Also I'm not sure these even exist. Certainly t= he > > > > Punit in current hardware doesn't deal with these. > > > > = > > > > Signed-off-by: Ville Syrj=E4l=E4 > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > > > drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ > > > > 2 files changed, 27 insertions(+) > > > > = > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915= /i915_reg.h > > > > index 3d1fef4..191df9e 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -525,6 +525,10 @@ enum punit_power_well { > > > > PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > > > > PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > > > > PUNIT_POWER_WELL_DPIO_CMN_D =3D 12, > > > > + /* FIXME: guesswork below */ > > > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 =3D 13, > > > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 =3D 14, > > > > + PUNIT_POWER_WELL_DPIO_RX2 =3D 15, > > > > = > > > > PUNIT_POWER_WELL_NUM, > > > > }; > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915= /intel_pm.c > > > > index cae936c..55f3e6b 100644 > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > > > > BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > > > BIT(POWER_DOMAIN_INIT)) > > > > = > > > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ > > > > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > > > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > > > + BIT(POWER_DOMAIN_INIT)) > > > > + > > > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ > > > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > > = > > > Atm, for all other ports we power up all lanes regardless of the actu= al > > > configuration (until the PHY side setup is proved to work fine). So f= or > > > consistency I'd do the same here too. With that change: > > = > > We do that here too. '.domains =3D 01 | 23' for both tx-d wells. Or am I > > missing something? > = > Ah, right I should've read a couple of lines below. So my above comment > can be ignored and my r-b applies as-is. > = > > > Reviewed-by: Imre Deak Queued for -next, thanks for the patch. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch