From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV Date: Tue, 29 Jul 2014 20:04:59 +0200 Message-ID: <20140729180459.GW4747@phenom.ffwll.local> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-35-git-send-email-ville.syrjala@linux.intel.com> <20140729100157.0d9618ab@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 722556E013 for ; Tue, 29 Jul 2014 11:04:51 -0700 (PDT) Received: by mail-wg0-f50.google.com with SMTP id n12so25959wgh.9 for ; Tue, 29 Jul 2014 11:04:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140729100157.0d9618ab@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote: > On Sat, 28 Jun 2014 02:04:25 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > CHV supports DP training pattern 3. Add the required stuff. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++---- > > 2 files changed, 16 insertions(+), 4 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 85b59c4..8debe61 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3515,6 +3515,8 @@ enum punit_power_well { > > #define DP_LINK_TRAIN_OFF (3 << 28) > > #define DP_LINK_TRAIN_MASK (3 << 28) > > #define DP_LINK_TRAIN_SHIFT 28 > > +#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) > > +#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) > > = > > /* CPT Link training mode */ > > #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index 739dc43..a825ff1 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_d= p, > > } > > = > > } else { > > - *DP &=3D ~DP_LINK_TRAIN_MASK; > > + if (IS_CHERRYVIEW(dev)) > > + *DP &=3D ~DP_LINK_TRAIN_MASK_CHV; > > + else > > + *DP &=3D ~DP_LINK_TRAIN_MASK; > > = > > switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > > case DP_TRAINING_PATTERN_DISABLE: > > @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_d= p, > > *DP |=3D DP_LINK_TRAIN_PAT_2; > > break; > > case DP_TRAINING_PATTERN_3: > > - DRM_ERROR("DP training pattern 3 not supported\n"); > > - *DP |=3D DP_LINK_TRAIN_PAT_2; > > + if (IS_CHERRYVIEW(dev)) { > > + *DP |=3D DP_LINK_TRAIN_PAT_3_CHV; > > + } else { > > + DRM_ERROR("DP training pattern 3 not supported\n"); > > + *DP |=3D DP_LINK_TRAIN_PAT_2; > > + } > > break; > > } > > } > > @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp) > > DP &=3D ~DP_LINK_TRAIN_MASK_CPT; > > I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); > > } else { > > - DP &=3D ~DP_LINK_TRAIN_MASK; > > + if (IS_CHERRYVIEW(dev)) > > + DP &=3D ~DP_LINK_TRAIN_MASK_CHV; > > + else > > + DP &=3D ~DP_LINK_TRAIN_MASK; > > I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); > > } > > POSTING_READ(intel_dp->output_reg); > = > I guess we could have a whole IS_CHV block, but that would probably add > more code than it saved... > = > Reviewed-by: Jesse Barnes This won't do a hole lot without adding HBR2 support ... Queued for -next anyway, thanks for the patch. -Daniel > = > -- = > Jesse Barnes, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch