From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/10] drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDW
Date: Tue, 29 Jul 2014 20:15:42 +0200 [thread overview]
Message-ID: <20140729181542.GZ4747@phenom.ffwll.local> (raw)
In-Reply-To: <1406653585-3352-6-git-send-email-damien.lespiau@intel.com>
On Tue, Jul 29, 2014 at 06:06:20PM +0100, Damien Lespiau wrote:
> Future platform will use config->ddi_pll_sel in a different way.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ea6ff71..bdbe8f7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -976,7 +976,7 @@ found:
> &pipe_config->dp_m2_n2);
> }
>
> - if (HAS_DDI(dev))
> + if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
> else
> intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
We could do an s/intel/gmch/ here too ... Or g4x.
-Daniel
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-07-29 18:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-29 17:06 [PATCH 00/10] Split the HSW/BDW PLL code a bit more Damien Lespiau
2014-07-29 17:06 ` [PATCH 01/10] drm/i915: Specify when the PLL hw state fields are valid Damien Lespiau
2014-07-29 17:06 ` [PATCH 02/10] drm/i915: Add a space to the shared DPLL debug message Damien Lespiau
2014-07-29 17:06 ` [PATCH 03/10] drm/i915: Extract the HSW DDI selection code into its own function Damien Lespiau
2014-07-29 17:06 ` [PATCH 04/10] drm/i915: Extract the HSW/BDW shared dpll init code Damien Lespiau
2014-07-29 17:06 ` [PATCH 05/10] drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDW Damien Lespiau
2014-07-29 18:15 ` Daniel Vetter [this message]
2014-07-29 17:06 ` [PATCH 06/10] drm/i915: Fix stale comment for intel_ddi_pll_select() Damien Lespiau
2014-07-29 17:06 ` [PATCH 07/10] drm/i915: Split the BDW/HSW specific shared pll selection Damien Lespiau
2014-07-29 17:06 ` [PATCH 08/10] drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specific Damien Lespiau
2014-07-29 17:06 ` [PATCH 09/10] drm/i915: Split the CDCLK retrieval per-platform Damien Lespiau
2014-07-29 17:06 ` [PATCH 10/10] drm/i915: Make ddi_clock_gate() HSW/BDW specific Damien Lespiau
2014-07-29 18:20 ` [PATCH 00/10] Split the HSW/BDW PLL code a bit more Daniel Vetter
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