From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 06/40] drm/i915: Add cdclk change support for chv Date: Tue, 29 Jul 2014 21:39:49 +0300 Message-ID: <20140729183949.GB4193@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-7-git-send-email-ville.syrjala@linux.intel.com> <20140729095103.09455821@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 78F7B6E3D2 for ; Tue, 29 Jul 2014 11:39:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140729095103.09455821@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote: > On Sat, 28 Jun 2014 02:03:57 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > Looks like the Punit is supposed to support the 400MHz cdclk directly on > > chv, so we don't need the vlv tricks. > > = > > FIXME: Punit doesn't seem ready for this yet on current hw > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 +++ > > drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++= ++++++-- > > 2 files changed, 52 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index f156591..e296312 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -491,6 +491,10 @@ > > #define BUNIT_REG_BISOC 0x11 > > = > > #define PUNIT_REG_DSPFREQ 0x36 > > +#define DSPFREQSTAT_SHIFT_CHV 24 > > +#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) > > +#define DSPFREQGUAR_SHIFT_CHV 8 > > +#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) > > #define DSPFREQSTAT_SHIFT 30 > > #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) > > #define DSPFREQGUAR_SHIFT 14 > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 99c10d1..9af1d13 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_devi= ce *dev, int cdclk) > > vlv_update_cdclk(dev); > > } > > = > > +static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) > > +{ > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + u32 val, cmd; > > + > > + WARN_ON(dev_priv->display.get_display_clock_speed(dev) !=3D dev_priv-= >vlv_cdclk_freq); > > + > > + switch (cdclk) { > > + case 400000: > > + cmd =3D 3; > > + break; > > + case 333333: > > + case 320000: > > + cmd =3D 2; > > + break; > > + case 266667: > > + cmd =3D 1; > > + break; > > + case 200000: > > + cmd =3D 0; > > + break; > > + default: > > + WARN_ON(1); > > + return; > > + } > > + > > + mutex_lock(&dev_priv->rps.hw_lock); > > + val =3D vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); > > + val &=3D ~DSPFREQGUAR_MASK_CHV; > > + val |=3D (cmd << DSPFREQGUAR_SHIFT_CHV); > > + vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); > > + if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & > > + DSPFREQSTAT_MASK_CHV) =3D=3D (cmd << DSPFREQSTAT_SHIFT_CHV), > > + 50)) { > > + DRM_ERROR("timed out waiting for CDclk change\n"); > > + } > > + mutex_unlock(&dev_priv->rps.hw_lock); > > + > > + vlv_update_cdclk(dev); > > +} > > + > > static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, > > int max_pixclk) > > { > > @@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(= struct drm_device *dev) > > int max_pixclk =3D intel_mode_max_pixclk(dev_priv); > > int req_cdclk =3D valleyview_calc_cdclk(dev_priv, max_pixclk); > > = > > - if (req_cdclk !=3D dev_priv->vlv_cdclk_freq) > > - valleyview_set_cdclk(dev, req_cdclk); > > + if (req_cdclk !=3D dev_priv->vlv_cdclk_freq) { > > + if (IS_CHERRYVIEW(dev)) > > + cherryview_set_cdclk(dev, req_cdclk); > > + else > > + valleyview_set_cdclk(dev, req_cdclk); > > + } > > + > > modeset_update_crtc_power_domains(dev); > > } > > = > = > Which doc has these Punit commands? I'm assuming you have them > correct, but a ref would be good if we don't already have one. These were in the punit has. The display cluster has still had the old vlv information last I looked. > = > Reviewed-by: Jesse Barnes > = > There should probably be a JIRA for this too so QA can verify once we > have updated punit support. > = > -- = > Jesse Barnes, Intel Open Source Technology Center -- = Ville Syrj=E4l=E4 Intel OTC