From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits Date: Tue, 29 Jul 2014 21:09:10 +0200 Message-ID: <20140729190910.GC4747@phenom.ffwll.local> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-13-git-send-email-ville.syrjala@linux.intel.com> <20140729095539.4451b239@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by gabe.freedesktop.org (Postfix) with ESMTP id C71116E341 for ; Tue, 29 Jul 2014 12:09:05 -0700 (PDT) Received: by mail-wi0-f180.google.com with SMTP id n3so1070166wiv.13 for ; Tue, 29 Jul 2014 12:09:01 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140729095539.4451b239@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 09:55:39AM -0700, Jesse Barnes wrote: > On Sat, 28 Jun 2014 02:04:03 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > CHV display PHY registes have two swing margin/deemph settings. Make it > > clear which ones we're using. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++-- > > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > > drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- > > 3 files changed, 10 insertions(+), 6 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index e296312..ba90320 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -831,8 +831,8 @@ enum punit_power_well { > > = > > #define _VLV_TX_DW2_CH0 0x8288 > > #define _VLV_TX_DW2_CH1 0x8488 > > -#define DPIO_SWING_MARGIN_SHIFT 16 > > -#define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) > > +#define DPIO_SWING_MARGIN000_SHIFT 16 > > +#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIF= T) > > #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 > > #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) > > = > > @@ -840,12 +840,16 @@ enum punit_power_well { > > #define _VLV_TX_DW3_CH1 0x848c > > /* The following bit for CHV phy */ > > #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) > > +#define DPIO_SWING_MARGIN101_SHIFT 16 > > +#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIF= T) > > #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) > > = > > #define _VLV_TX_DW4_CH0 0x8290 > > #define _VLV_TX_DW4_CH1 0x8490 > > #define DPIO_SWING_DEEMPH9P5_SHIFT 24 > > #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIF= T) > > +#define DPIO_SWING_DEEMPH6P0_SHIFT 16 > > +#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIF= T) > > #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) > > = > > #define _VLV_TX3_DW4_CH0 0x690 > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index e272f92..4457f8f 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct in= tel_dp *intel_dp) > > /* Program swing margin */ > > for (i =3D 0; i < 4; i++) { > > val =3D vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); > > - val &=3D ~DPIO_SWING_MARGIN_MASK; > > - val |=3D margin_reg_value << DPIO_SWING_MARGIN_SHIFT; > > + val &=3D ~DPIO_SWING_MARGIN000_MASK; > > + val |=3D margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; > > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); > > } > > = > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/i= ntel_hdmi.c > > index c9d77d3..c5c88127 100644 > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > @@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_enco= der *encoder) > > = > > for (i =3D 0; i < 4; i++) { > > val =3D vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); > > - val &=3D ~DPIO_SWING_MARGIN_MASK; > > - val |=3D 102 << DPIO_SWING_MARGIN_SHIFT; > > + val &=3D ~DPIO_SWING_MARGIN000_MASK; > > + val |=3D 102 << DPIO_SWING_MARGIN000_SHIFT; > > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); > > } > > = > = > Reviewed-by: Jesse Barnes Ok, pulled in the pile of patches Jesse just reviewed. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch