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From: Daniel Vetter <daniel@ffwll.ch>
To: "Barbalho, Rafael" <rafael.barbalho@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 16/40] drm/i915: Add chv_power_wells[]
Date: Wed, 30 Jul 2014 13:18:08 +0200	[thread overview]
Message-ID: <20140730111808.GM4747@phenom.ffwll.local> (raw)
In-Reply-To: <4B498744C37F034EA16F6FBC6AB9FAD21AE5362E@IRSMSX103.ger.corp.intel.com>

On Fri, Jul 11, 2014 at 02:09:40PM +0000, Barbalho, Rafael wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of ville.syrjala@linux.intel.com
> > Sent: Saturday, June 28, 2014 12:04 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 16/40] drm/i915: Add chv_power_wells[]
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add chv_power_wells[] so we can start to build up the power well support
> > for chv. Just the "always on" well there initialy.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 898654f..e2b956e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6498,6 +6498,15 @@ static struct i915_power_well vlv_power_wells[] =
> > {
> >  	},
> >  };
> > 
> > +static struct i915_power_well chv_power_wells[] = {
> > +	{
> > +		.name = "always-on",
> > +		.always_on = 1,
> > +		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
> > +		.ops = &i9xx_always_on_power_well_ops,
> > +	},
> > +};
> > +
> >  static struct i915_power_well *lookup_power_well(struct drm_i915_private
> > *dev_priv,
> >  						 enum punit_power_well
> > power_well_id)
> >  {
> > @@ -6534,6 +6543,8 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> >  	} else if (IS_BROADWELL(dev_priv->dev)) {
> >  		set_power_wells(power_domains, bdw_power_wells);
> >  		hsw_pwr = power_domains;
> > +	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> > +		set_power_wells(power_domains, chv_power_wells);
> >  	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
> >  		set_power_wells(power_domains, vlv_power_wells);
> >  	} else {
> > --
> > 1.8.5.5
> > 
> 
> Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>

Ok, pulled this one in too to undo my giant merge fumble. My apologies to
everyone for the mess.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2014-07-30 11:18 UTC|newest]

Thread overview: 109+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-27 23:03 [PATCH 00/40] CHV stuff mostly ville.syrjala
2014-06-27 23:03 ` [PATCH 01/40] drm/i915: Try to populate mem_freq for chv ville.syrjala
2014-07-12 13:27   ` Deepak S
2014-06-27 23:03 ` [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code ville.syrjala
2014-07-12 13:30   ` Deepak S
2014-07-11 14:04     ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values ville.syrjala
2014-07-12 13:46   ` Deepak S
2014-07-28 15:17     ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave() ville.syrjala
2014-06-27 23:03 ` [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev ville.syrjala
2014-07-12 13:48   ` Deepak S
2014-07-11 13:59     ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 06/40] drm/i915: Add cdclk change support for chv ville.syrjala
2014-07-29 16:51   ` Jesse Barnes
2014-07-29 17:59     ` Daniel Vetter
2014-07-29 18:07       ` Jesse Barnes
2014-07-29 18:39     ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready ville.syrjala
2014-07-29 16:51   ` Jesse Barnes
2014-06-27 23:03 ` [PATCH 08/40] drm/i915: Leave DPLL ref clocks on ville.syrjala
2014-07-29 16:51   ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 09/40] drm/i915: Split chv_update_pll() apart ville.syrjala
2014-07-29 16:53   ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 10/40] drm/i915: Call encoder->post_disable() in intel_sanitize_encoder() ville.syrjala
2014-07-11 14:46   ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv ville.syrjala
2014-07-29 16:54   ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits ville.syrjala
2014-07-29 16:55   ` Jesse Barnes
2014-07-29 19:09     ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 13/40] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv ville.syrjala
2014-06-27 23:04 ` [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master " ville.syrjala
2014-07-29 16:57   ` Jesse Barnes
2014-08-01 13:10     ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits " ville.syrjala
2014-08-01 13:23   ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 16/40] drm/i915: Add chv_power_wells[] ville.syrjala
2014-07-11 14:09   ` Barbalho, Rafael
2014-07-30 11:18     ` Daniel Vetter [this message]
2014-06-27 23:04 ` [PATCH 17/40] drm/i915: Add chv cmnlane power wells ville.syrjala
2014-07-25 11:55   ` Imre Deak
2014-07-28 15:18     ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 18/40] drm/i915: Kill intel_reset_dpio() ville.syrjala
2014-07-25 11:56   ` Imre Deak
2014-06-27 23:04 ` [PATCH 19/40] drm/i915: Add disp2d power well for chv ville.syrjala
2014-07-25 13:23   ` Imre Deak
2014-06-27 23:04 ` [PATCH 20/40] drm/i915: Add per-pipe power wells " ville.syrjala
2014-07-25 13:24   ` Imre Deak
2014-06-27 23:04 ` [PATCH 21/40] drm/i915: Add chv port B and C TX wells ville.syrjala
2014-07-25 13:25   ` Imre Deak
2014-06-27 23:04 ` [PATCH 22/40] drm/i915: Add chv port D " ville.syrjala
2014-07-25 13:30   ` Imre Deak
2014-07-28  9:11     ` Daniel Vetter
2014-07-28 15:19     ` Ville Syrjälä
2014-07-29  9:54       ` Imre Deak
2014-07-29 10:27         ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV ville.syrjala
2014-07-31 15:08   ` Paulo Zanoni
2014-07-31 15:16     ` Ville Syrjälä
2014-07-31 17:05       ` Paulo Zanoni
2014-07-31 17:13         ` Ville Syrjälä
2014-07-31 18:06           ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values ville.syrjala
2014-07-31 18:08   ` Paulo Zanoni
2014-08-01 12:33     ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines ville.syrjala
2014-07-31 20:16   ` Paulo Zanoni
2014-08-01 11:26     ` Ville Syrjälä
2014-08-01 12:28     ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers ville.syrjala
2014-07-30 20:43   ` Paulo Zanoni
2014-07-31 12:05     ` Ville Syrjälä
2014-07-31 12:11     ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 27/40] drm/i915: Split a few long debug prints ville.syrjala
2014-07-29 16:59   ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 28/40] drm/i915: Add cherryview_update_wm() ville.syrjala
2014-07-31 20:57   ` Paulo Zanoni
2014-08-01 11:33     ` Ville Syrjälä
2014-08-01 12:36     ` [PATCH v2 " ville.syrjala
2014-08-01 14:29       ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper ville.syrjala
2014-07-29 16:59   ` Jesse Barnes
2014-07-29 18:01     ` Daniel Vetter
2014-07-30 20:23       ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround ville.syrjala
2014-07-11 13:30   ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 31/40] drm/i916: Init chv workarounds at render ring init ville.syrjala
2014-07-30 12:35   ` Barbalho, Rafael
2014-07-30 12:48     ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv ville.syrjala
2014-07-30 12:12   ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros ville.syrjala
2014-07-30 12:13   ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV ville.syrjala
2014-07-29 17:01   ` Jesse Barnes
2014-07-29 18:04     ` Daniel Vetter
2014-07-29 18:34       ` Ville Syrjälä
2014-07-29 19:12         ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 35/40] drm/i915: Fix vdd locking ville.syrjala
2014-06-27 23:04 ` [PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off ville.syrjala
2014-06-27 23:04 ` [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes ville.syrjala
2014-06-30 21:52   ` Jesse Barnes
2014-07-29 18:06     ` Daniel Vetter
2014-07-29 19:18       ` Ville Syrjälä
2014-07-29 19:23         ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer ville.syrjala
2014-06-27 23:04 ` [PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions ville.syrjala
2014-06-27 23:04 ` [PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port ville.syrjala

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