From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 26/40] drm/i915: Parametrize VLV_DDL
	registers
Date: Thu, 31 Jul 2014 15:05:56 +0300
Message-ID: <20140731120556.GK4193@intel.com>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Wed, Jul 30, 2014 at 05:43:10PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >
> > The VLV/CHV DDL registers are uniform, and neatly enough the register
> > offsets are sane so we can easily unify them to a single set of defines
> > and just pass the pipe as the parameter to compute the register offset.
> =

> What the commit message doesn't tell is that now we will call
> vlv_compute_drain_latency() for pipe C on CHV since I see CHV is
> defined with num_pipes=3D3. I think this is quite an important detail,
> since it's the only way this patch changes the behavior of the code.
> =

> If that is intentional and correct, then I suggest amending the commit
> message, even maybe the patch title. Then you can add: Reviewed-by:
> Paulo Zanoni <paulo.r.zanoni@intel.com>.

One of the following patches will add a proper cherryview_update_wm()
function which also fills out the actual watermarks for pipe C. Ideally
I probably should have reordered these patches. But I'll add a note
of some sort here to avoid bigger reordering pains now.

-- =

Ville Syrj=E4l=E4
Intel OTC