From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Introduce FBC False Color for debug purposes. Date: Fri, 1 Aug 2014 13:27:49 +0300 Message-ID: <20140801102749.GT4193@intel.com> References: <20140731040127.GB1284@bwidawsk.net> <1406833642-2753-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id CB64489E9E for ; Fri, 1 Aug 2014 03:30:17 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406833642-2753-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 31, 2014 at 12:07:22PM -0700, Rodrigo Vivi wrote: > With this bit enabled, HW changes the color when compressing frames for > debug purposes. > = > ALthough the simple way to enable a single bit is over intel_reg_write, > this value is overwriten on next update_fbc so depending on the workload > it is not possible to set this bit with intel-gpu-tools. So this patch > introduces a persistent way to enable false color over debugfs. > = > v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested > v3: (Ville) only do false color for IVB+ since according to spec bit is > MBZ before IVB. > v4: We don't have FBC on valleyview nor on cherryview (Ben) > = > Reviewed-by: Ben Widawsky > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_debugfs.c | 42 +++++++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 4 files changed, 48 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i= 915_debugfs.c > index 9e737b7..2147b41 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, voi= d *unused) > return 0; > } > = > +static int i915_fbc_fc_get(void *data, u64 *val) > +{ > + struct drm_device *dev =3D data; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + > + if (INTEL_INFO(dev)->gen < 7 || !HAS_PCH_SPLIT(dev)) Better use HAS_FBC() > + return -ENODEV; > + > + drm_modeset_lock_all(dev); > + *val =3D dev_priv->fbc.false_color; > + drm_modeset_unlock_all(dev); > + > + return 0; > +} > + > +static int i915_fbc_fc_set(void *data, u64 val) > +{ > + struct drm_device *dev =3D data; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + u32 reg; > + > + if (INTEL_INFO(dev)->gen < 7 || !HAS_PCH_SPLIT(dev)) > + return -ENODEV; > + > + drm_modeset_lock_all(dev); > + > + reg =3D I915_READ(ILK_DPFC_CONTROL); > + dev_priv->fbc.false_color =3D val; > + > + I915_WRITE(ILK_DPFC_CONTROL, val ? > + (reg | FBC_CTL_FALSE_COLOR) : > + (reg & ~FBC_CTL_FALSE_COLOR)); > + > + drm_modeset_unlock_all(dev); > + return 0; > +} > + > +DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, > + i915_fbc_fc_get, i915_fbc_fc_set, > + "%llu\n"); > + > static int i915_ips_status(struct seq_file *m, void *unused) > { > struct drm_info_node *node =3D m->private; > @@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files { > {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, > {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, > {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, > + {"i915_fbc_false_color", &i915_fbc_fc_fops}, > }; > = > void intel_display_crc_init(struct drm_device *dev) > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index d604f4f..3a29f9e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -636,6 +636,8 @@ struct i915_fbc { > struct drm_mm_node compressed_fb; > struct drm_mm_node *compressed_llb; > = > + bool false_color; > + > struct intel_fbc_work { > struct delayed_work work; > struct drm_crtc *crtc; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 28e21ed..b5d295a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1540,6 +1540,7 @@ enum punit_power_well { > /* Framebuffer compression for Ironlake */ > #define ILK_DPFC_CB_BASE 0x43200 > #define ILK_DPFC_CONTROL 0x43208 > +#define FBC_CTL_FALSE_COLOR (1<<10) > /* The bit 28-8 is reserved */ > #define DPFC_RESERVED (0x1FFFFF00) > #define ILK_DPFC_RECOMP_CTL 0x4320c > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 1ddd4df..338a80b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > = > dpfc_ctl |=3D IVB_DPFC_CTL_FENCE_EN; > = > + if (dev_priv->fbc.false_color) > + dpfc_ctl |=3D FBC_CTL_FALSE_COLOR; > + > I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); > = > if (IS_IVYBRIDGE(dev)) { > -- = > 1.9.3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC