From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values Date: Fri, 1 Aug 2014 15:33:25 +0300 Message-ID: <20140801123325.GZ4193@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-25-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B88A6E74E for ; Fri, 1 Aug 2014 05:33:29 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Paulo Zanoni Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 31, 2014 at 03:08:29PM -0300, Paulo Zanoni wrote: > 2014-06-27 20:04 GMT-03:00 : > > From: Ville Syrj=E4l=E4 > > > > The DDL registers can hold 7bit numbers. Make the most of those seven > > bits by adjusting the threshold where we switch between the 64 vs. 32 > > precision multipliers. > > > > Also we compute 'entries' to make the decision about precision, and then > > we recompute the same value to calculate the actual drain latency. Just > > use the already calculate 'entries' there. > = > Just an addition: don't we also want to WARN in case "entires < 64" > (or in case the final result exceeds 7 bits, which is equivalent)? > Could be a separate patch too. Yeah we could WARN when things go south. But there are some patches from = Gajanan pending that touch this code too, so probably best to wait until those have gone in to avoid too much rebase pain. > = > With or without that: Reviewed-by: Paulo Zanoni > = > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_pm.c | 9 ++++----- > > 1 file changed, 4 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 9413184..3aa7959 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct dr= m_device *dev, > > pixel_size =3D crtc->primary->fb->bits_per_pixel / 8; /* BP= P */ > > > > entries =3D (clock / 1000) * pixel_size; > > - *plane_prec_mult =3D (entries > 256) ? > > + *plane_prec_mult =3D (entries > 128) ? > > DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > > - *plane_dl =3D (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * > > - pixel_size); > > + *plane_dl =3D (64 * (*plane_prec_mult) * 4) / entries; > > > > entries =3D (clock / 1000) * 4; /* BPP is always 4 for cursor= */ > > - *cursor_prec_mult =3D (entries > 256) ? > > + *cursor_prec_mult =3D (entries > 128) ? > > DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > > - *cursor_dl =3D (64 * (*cursor_prec_mult) * 4) / ((clock / 1000)= * 4); > > + *cursor_dl =3D (64 * (*cursor_prec_mult) * 4) / entries; > > > > return true; > > } > > -- > > 1.8.5.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > = > = > -- = > Paulo Zanoni -- = Ville Syrj=E4l=E4 Intel OTC