From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv Date: Fri, 1 Aug 2014 16:10:14 +0300 Message-ID: <20140801131014.GA4193@intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-15-git-send-email-ville.syrjala@linux.intel.com> <20140729095709.4322ea1a@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id C63A76E224 for ; Fri, 1 Aug 2014 06:12:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140729095709.4322ea1a@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 09:57:09AM -0700, Jesse Barnes wrote: > On Sat, 28 Jun 2014 02:04:05 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > Just an attempt to frob these bits. Apparently we should not need to > > touch them (apart from maybe making sure the override is disabled so > > that the hardware automagically does the right thing). > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > > drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++++ > > 3 files changed, 58 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 2a7bc22..d246609 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -758,6 +758,8 @@ enum punit_power_well { > > #define _VLV_PCS_DW0_CH1 0x8400 > > #define DPIO_PCS_TX_LANE2_RESET (1<<16) > > #define DPIO_PCS_TX_LANE1_RESET (1<<7) > > +#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) > > +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) > > #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) > > = > > #define _VLV_PCS01_DW0_CH0 0x200 > > @@ -834,8 +836,18 @@ enum punit_power_well { > > = > > #define _VLV_PCS_DW11_CH0 0x822c > > #define _VLV_PCS_DW11_CH1 0x842c > > +#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) > > +#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) > > +#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) > > #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH= 1) > > = > > +#define _VLV_PCS01_DW11_CH0 0x022c > > +#define _VLV_PCS23_DW11_CH0 0x042c > > +#define _VLV_PCS01_DW11_CH1 0x262c > > +#define _VLV_PCS23_DW11_CH1 0x282c > > +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW= 0_CH1) > > +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW= 0_CH1) > > + > > #define _VLV_PCS_DW12_CH0 0x8230 > > #define _VLV_PCS_DW12_CH1 0x8430 > > #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH= 1) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index c59e8fc..814a950 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encod= er *encoder) > > = > > mutex_lock(&dev_priv->dpio_lock); > > = > > + /* TX FIFO reset source */ > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); > > + val |=3D DPIO_LEFT_TXFIFO_RST_MASTER2; > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER2; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER; > > + val &=3D ~DPIO_RIGHT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_LANEDESKEW_STRAP_OVRD; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER2; > > + val &=3D ~DPIO_RIGHT_TXFIFO_RST_MASTER2; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_RIGHT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_LANEDESKEW_STRAP_OVRD; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); > > + > > /* Deassert soft data lane reset*/ > > val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); > > val |=3D CHV_PCS_REQ_SOFTRESET_EN; > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/i= ntel_hdmi.c > > index cda6506..47430d5 100644 > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > @@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_enc= oder *encoder) > > = > > mutex_lock(&dev_priv->dpio_lock); > > = > > + /* TX FIFO reset source */ > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); > > + val |=3D DPIO_LEFT_TXFIFO_RST_MASTER2; > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER2; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER; > > + val &=3D ~DPIO_RIGHT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_LANEDESKEW_STRAP_OVRD; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER2; > > + val &=3D ~DPIO_RIGHT_TXFIFO_RST_MASTER2; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); > > + > > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); > > + val &=3D ~DPIO_LEFT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_RIGHT_TXFIFO_RST_MASTER; > > + val |=3D DPIO_LANEDESKEW_STRAP_OVRD; > > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); > > + > > /* Deassert soft data lane reset*/ > > val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); > > val |=3D CHV_PCS_REQ_SOFTRESET_EN; > = > Did this actually make a difference? Would be nice to get some > clarification from the phy guys on this and update our docs... No. The problems I was having were caused by the other problems (pps and missing DP/HDMI port register writes). So in the next patch I just went ahead and cleared the reset override bits. So I think we should just squash these two patches and be happy with the result. I'll post a squashed patch... -- = Ville Syrj=E4l=E4 Intel OTC