From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: FBC flush nuke for BDW Date: Mon, 4 Aug 2014 10:11:47 +0200 Message-ID: <20140804081147.GL8727@phenom.ffwll.local> References: <1406737578-14498-2-git-send-email-rodrigo.vivi@intel.com> <1406833664-2870-1-git-send-email-rodrigo.vivi@intel.com> <20140801140729.GB4193@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by gabe.freedesktop.org (Postfix) with ESMTP id DECB289CD7 for ; Mon, 4 Aug 2014 01:11:36 -0700 (PDT) Received: by mail-wi0-f169.google.com with SMTP id n3so5800745wiv.0 for ; Mon, 04 Aug 2014 01:11:33 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140801140729.GB4193@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 01, 2014 at 05:07:30PM +0300, Ville Syrj=E4l=E4 wrote: > On Thu, Jul 31, 2014 at 12:07:44PM -0700, Rodrigo Vivi wrote: > > According to spec FBC on BDW and HSW are identical without any gaps. > > So let's copy the nuke and let FBC really start compressing stuff. > > = > > Without this patch we can verify with false color that nothing is being > > compressed. With the nuke in place and false color it is possible > > to see false color debugs. > > = > > v2: Fix rebase conflict. > > = > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/= i915/intel_ringbuffer.c > > index 2908896..4ba3db1 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -406,6 +406,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, > > { > > u32 flags =3D 0; > > u32 scratch_addr =3D ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; > > + int ret; > > = > > flags |=3D PIPE_CONTROL_CS_STALL; > > = > > @@ -424,7 +425,14 @@ gen8_render_ring_flush(struct intel_engine_cs *rin= g, > > flags |=3D PIPE_CONTROL_GLOBAL_GTT_IVB; > > } > > = > > - return gen8_emit_pipe_control(ring, flags, scratch_addr); > > + ret =3D gen8_emit_pipe_control(ring, flags, scratch_addr); > > + if (ret) > > + return ret; > > + > > + if (!invalidate_domains && flush_domains) > > + return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); > > + > > + return 0; > > } > > = > > static void ring_write_tail(struct intel_engine_cs *ring, > > @@ -2065,7 +2073,7 @@ static int gen6_ring_flush(struct intel_engine_cs= *ring, > > } > > intel_ring_advance(ring); > > = > > - if (IS_GEN7(dev) && !invalidate && flush) > > + if (INTEL_INFO(dev)->gen >=3D 7 && !invalidate && flush) > > return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); > = > Apparently BDW has problems with LRIs to certain register offsets on > !RCS and this here would hit that. The suggested workaround is to emit > such LRIs only from RCS. Doing that would also involve tossing in a > semaphore, so it feels like something that ought to be handled > somewhere a bit higher up. *cough* sw frontbuffer tracking *cough* At least with fbc we have this nice igt test already. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch