From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/3] drm/i915: Generalize drain latency computation Date: Mon, 4 Aug 2014 17:41:46 +0300 Message-ID: <20140804144146.GG4193@intel.com> References: <1405515245-14946-1-git-send-email-gajanan.bhat@intel.com> <1405515245-14946-3-git-send-email-gajanan.bhat@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id D29B789B11 for ; Mon, 4 Aug 2014 07:41:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1405515245-14946-3-git-send-email-gajanan.bhat@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Gajanan Bhat Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jul 16, 2014 at 06:24:04PM +0530, Gajanan Bhat wrote: > Modify drain latency computation to use it for any plane. Same function c= an be > used for primary, cursor and sprite planes. > = > Signed-off-by: Gajanan Bhat > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 82 ++++++++++++++++++++++-----------= ------ > 2 files changed, 47 insertions(+), 36 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index d2a220b..a1260a2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3877,6 +3877,7 @@ enum punit_power_well { > #define DDL_PLANE_PRECISION_64 (1<<7) > #define DDL_PLANE_PRECISION_32 (0<<7) > #define DDL_PLANE_SHIFT 0 > +#define DRAIN_LATENCY_MAX 0x7f > = > /* FIFO watermark sizes etc */ > #define G4X_FIFO_LINE_SIZE 64 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 90df1e8..f3a3e90 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1268,33 +1268,21 @@ static bool g4x_compute_srwm(struct drm_device *d= ev, > display, cursor); > } > = > -static bool vlv_compute_drain_latency(struct drm_device *dev, > - int plane, > - int *plane_prec_mult, > - int *plane_dl, > - int *cursor_prec_mult, > - int *cursor_dl) > +static bool vlv_compute_drain_latency(struct drm_crtc *crtc, > + int pixel_size, > + int *prec_mult, > + int *drain_latency) > { > - struct drm_crtc *crtc; > - int clock, pixel_size; > int entries; > + int clock =3D to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; > = > - crtc =3D intel_get_crtc_for_plane(dev, plane); > - if (!intel_crtc_active(crtc)) > + if (clock =3D=3D 0 || pixel_size =3D=3D 0) > return false; > = > - clock =3D to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; > - pixel_size =3D crtc->primary->fb->bits_per_pixel / 8; /* BPP */ > - > - entries =3D (clock / 1000) * pixel_size; > - *plane_prec_mult =3D (entries > 128) ? > - DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > - *plane_dl =3D (64 * (*plane_prec_mult) * 4) / entries; > - > - entries =3D (clock / 1000) * 4; /* BPP is always 4 for cursor */ > - *cursor_prec_mult =3D (entries > 128) ? > - DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > - *cursor_dl =3D (64 * (*cursor_prec_mult) * 4) / entries; > + entries =3D DIV_ROUND_UP(clock, 1000) * pixel_size; Yeah rounding the clock up should be safe, rounding down not so much. But this change should really be a separate patch. > + *prec_mult =3D (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : > + DRAIN_LATENCY_PRECISION_32; > + *drain_latency =3D (64 * (*prec_mult) * 4) / entries; Another thing you could fix is making sure the result is <=3D0x7f. It's quite possible we'd exceed that (all that's needed is a 16bpp fb and <32MHz pixel clock, which isn't all that far fetched). This could be part of the rounding fix patch since it's somewhat related. > = > return true; > } > @@ -1309,24 +1297,46 @@ static bool vlv_compute_drain_latency(struct drm_= device *dev, > = > static void vlv_update_drain_latency(struct drm_crtc *crtc) > { > - struct drm_device *dev =3D crtc->dev; > - struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct drm_i915_private *dev_priv =3D crtc->dev->dev_private; > + int pixel_size; > + int drain_latency; > enum pipe pipe =3D to_intel_crtc(crtc)->pipe; > - int plane_prec, plane_dl; > - int cursor_prec, cursor_dl; > - int plane_prec_mult, cursor_prec_mult; > + int plane_prec, prec_mult, plane_dl; > = > - if (vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl, > - &cursor_prec_mult, &cursor_dl)) { > - cursor_prec =3D (cursor_prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > - DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32; > - plane_prec =3D (plane_prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > - DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32; > + plane_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_PLANE_PRECISION_64 & > + ~DRAIN_LATENCY_MAX & ~DDL_CURSOR_PRECISION_64 & > + ~(DRAIN_LATENCY_MAX << DDL_CURSOR_SHIFT); > = > - I915_WRITE(VLV_DDL(pipe), cursor_prec | > - (cursor_dl << DDL_CURSOR_SHIFT) | > - plane_prec | (plane_dl << DDL_PLANE_SHIFT)); > + if (!intel_crtc_active(crtc)) { > + I915_WRITE(VLV_DDL(pipe), plane_dl); > + return; > } > + > + /* Primary plane Drain Latency */ > + pixel_size =3D crtc->primary->fb->bits_per_pixel / 8; /* BPP */ > + if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_late= ncy)) { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_PLANE_PRECISION_64 : > + DDL_PLANE_PRECISION_32; > + plane_dl =3D plane_dl | plane_prec | drain_latency; > + } > + > + /* Cursor Drain Latency > + * BPP is always 4 for cursor > + */ > + pixel_size =3D 4; > + > + /* Program cursor DL only if it is enabled */ > + if ((I915_READ(CURCNTR(pipe)) & CURSOR_MODE) && > + vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_late= ncy)) { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_CURSOR_PRECISION_64 : > + DDL_CURSOR_PRECISION_32; > + plane_dl =3D plane_dl | plane_prec | > + drain_latency << DDL_CURSOR_SHIFT; > + } > + > + I915_WRITE(VLV_DDL(pipe), plane_dl); > } > = > #define single_plane_enabled(mask) is_power_of_2(mask) > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC