From: Daniel Vetter <daniel@ffwll.ch>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/7] drm/i915: avoid emiting semaphore wait on GEN8 when seqno wrap happened.
Date: Tue, 5 Aug 2014 10:36:44 +0200 [thread overview]
Message-ID: <20140805083644.GE8727@phenom.ffwll.local> (raw)
In-Reply-To: <1407176119-5294-5-git-send-email-rodrigo.vivi@intel.com>
On Mon, Aug 04, 2014 at 11:15:17AM -0700, Rodrigo Vivi wrote:
This commit message is too thin.
> C: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Does this blow up with Mika's seqno wrap testcase? If so please add the
right Testcase: line, if not, how can we repro this?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 30 +++++++++++++++++++++---------
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2e566e0..cd30b39 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -867,15 +867,26 @@ gen8_ring_sync(struct intel_engine_cs *waiter,
> if (ret)
> return ret;
>
> - intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
> - MI_SEMAPHORE_GLOBAL_GTT |
> - MI_SEMAPHORE_POLL |
> - MI_SEMAPHORE_SAD_GTE_SDD);
> - intel_ring_emit(waiter, seqno);
> - intel_ring_emit(waiter,
> - lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
> - intel_ring_emit(waiter,
> - upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
> + /* If seqno wrap happened, omit the wait with no-ops */
> + if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
> + intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_GLOBAL_GTT |
> + MI_SEMAPHORE_POLL |
> + MI_SEMAPHORE_SAD_GTE_SDD);
> + intel_ring_emit(waiter, seqno);
> + intel_ring_emit(waiter,
> + lower_32_bits(GEN8_WAIT_OFFSET(waiter,
> + signaller->id)));
> + intel_ring_emit(waiter,
> + upper_32_bits(GEN8_WAIT_OFFSET(waiter,
> + signaller->id)));
> + } else {
> + intel_ring_emit(waiter, MI_NOOP);
> + intel_ring_emit(waiter, MI_NOOP);
> + intel_ring_emit(waiter, MI_NOOP);
> + intel_ring_emit(waiter, MI_NOOP);
> + }
> +
> intel_ring_advance(waiter);
> return 0;
> }
> @@ -2572,6 +2583,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
> ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
> ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
> +
> }
> }
> ring->init = init_ring_common;
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-08-05 8:36 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-04 18:15 [PATCH 1/7] drm/i915/bdw: Always issue a force restore Rodrigo Vivi
2014-08-04 18:15 ` [PATCH 2/7] drm/i915: Add thread stall DOP clock gating workaround on Broadwell Rodrigo Vivi
2014-08-05 17:10 ` Ville Syrjälä
2014-08-04 18:15 ` [PATCH 3/7] drm/i915/bdw: MI_FLUSH_DW a qword instead of dword Rodrigo Vivi
2014-08-05 1:21 ` Ben Widawsky
2014-08-04 18:15 ` [PATCH 4/7] drm/i915/bdw: cs-stall before state cache invld w/a Rodrigo Vivi
2014-08-05 12:39 ` Ville Syrjälä
2014-08-04 18:15 ` [PATCH 5/7] drm/i915: avoid emiting semaphore wait on GEN8 when seqno wrap happened Rodrigo Vivi
2014-08-05 8:36 ` Daniel Vetter [this message]
2014-08-04 18:15 ` [PATCH 6/7] drm/i915: BDW Semaphore signal with Post Sync Rodrigo Vivi
2014-08-04 18:15 ` [PATCH 7/7] Revert "drm/i915: Enable semaphores on BDW" Rodrigo Vivi
2014-08-07 20:05 ` Rodrigo Vivi
2014-08-08 7:10 ` Daniel Vetter
2014-08-08 7:13 ` Daniel Vetter
2014-08-08 7:31 ` Chris Wilson
2014-08-05 1:20 ` [PATCH 1/7] drm/i915/bdw: Always issue a force restore Ben Widawsky
2014-08-05 8:41 ` Daniel Vetter
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