From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/7] drm/i915/bdw: cs-stall before state cache invld w/a Date: Tue, 5 Aug 2014 15:39:40 +0300 Message-ID: <20140805123940.GI4193@intel.com> References: <1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com> <1407176119-5294-4-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 295596E1C5 for ; Tue, 5 Aug 2014 05:40:13 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1407176119-5294-4-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org, Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Mon, Aug 04, 2014 at 11:15:16AM -0700, Rodrigo Vivi wrote: > From: Ben Widawsky > = > We do this already for previous GENs. I guess we must do it for BDW too > according to DOCS. > = > "Pipe_control with CS-stall bit set must be issued before a > pipe-control command that has the State Cache Invalidate bit set." > = > This does not solve the problem I have unfortunately. > = > I didn't check if this was in Ville's CHV series. If it was, I > apologize. Ken's version from long ago was included there. It's just waiting to be merged. > = > NOTE: I tried to use smaller lengths for the command, but nothing made > it happy except 6. > = > Cc: Kenneth Graunke > Cc: Jordan Justen > Signed-off-by: Ben Widawsky > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 9a562b5..2e566e0 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -279,17 +279,25 @@ gen6_render_ring_flush(struct intel_engine_cs *ring, > static int > gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) > { > - int ret; > + int ret, size =3D 4; > = > - ret =3D intel_ring_begin(ring, 4); > + if (IS_BROADWELL(ring->dev)) > + size +=3D 2; > + > + ret =3D intel_ring_begin(ring, size); > if (ret) > return ret; > = > - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size)); > intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_STALL_AT_SCOREBOARD); > intel_ring_emit(ring, 0); > intel_ring_emit(ring, 0); > + if (IS_BROADWELL(ring->dev)) { > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, 0); > + } > + > intel_ring_advance(ring); > = > return 0; > @@ -422,6 +430,11 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, > flags |=3D PIPE_CONTROL_STATE_CACHE_INVALIDATE; > flags |=3D PIPE_CONTROL_QW_WRITE; > flags |=3D PIPE_CONTROL_GLOBAL_GTT_IVB; > + > + /* Workaround: we must issue a pipe_control with CS-stall bit > + * set before a pipe_control command that has the state cache > + * invalidate bit set. */ > + gen7_render_ring_cs_stall_wa(ring); > } > = > return gen8_emit_pipe_control(ring, flags, scratch_addr); > -- = > 1.9.3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC