From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Round-up clock and limit drain latency Date: Tue, 5 Aug 2014 15:46:25 +0300 Message-ID: <20140805124625.GJ4193@intel.com> References: <20140804144146.GG4193@intel.com> <1407260754-18316-1-git-send-email-gajanan.bhat@intel.com> <1407260754-18316-2-git-send-email-gajanan.bhat@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 532356E14E for ; Tue, 5 Aug 2014 05:46:29 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1407260754-18316-2-git-send-email-gajanan.bhat@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Gajanan Bhat Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 05, 2014 at 11:15:54PM +0530, Gajanan Bhat wrote: > Round up clock computation and limit drain latency to maximum of 0x7F. > = > Signed-off-by: Gajanan Bhat > --- > drivers/gpu/drm/i915/intel_pm.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index ea64675..5e81c49 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1285,11 +1285,14 @@ static bool vlv_compute_drain_latency(struct drm_= crtc *crtc, > if (WARN(pixel_size =3D=3D 0, "Pixel size is zero!\n")) > return false; > = > - entries =3D (clock / 1000) * pixel_size; > + entries =3D DIV_ROUND_UP(clock, 1000) * pixel_size; > *prec_mult =3D (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : > DRAIN_LATENCY_PRECISION_32; > *drain_latency =3D (64 * (*prec_mult) * 4) / entries; > = > + if (*drain_latency > DRAIN_LATENCY_MASK) > + *drain_latency =3D DRAIN_LATENCY_MASK; I would have probably written this as: *drain_latency =3D min(..., DRAIN_LATENCY_MASK); But that's just a style I like. The patch looks fine to me so: Reviewed-by: Ville Syrj=E4l=E4 > + > return true; > } > = > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC