From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeff McGee Subject: Re: [PATCH 2/2] drm/i915/chv: Implement SSEU info for CHV Date: Tue, 5 Aug 2014 08:47:54 -0500 Message-ID: <20140805134754.GC4660@jeffdesk> References: <1406771987-1127-1-git-send-email-jeff.mcgee@intel.com> <1406771987-1127-2-git-send-email-jeff.mcgee@intel.com> <20140804082255.GQ8727@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 701546E1EB for ; Tue, 5 Aug 2014 06:37:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140804082255.GQ8727@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Aug 04, 2014 at 10:22:55AM +0200, Daniel Vetter wrote: > On Wed, Jul 30, 2014 at 08:59:47PM -0500, jeff.mcgee@intel.com wrote: > > From: Jeff McGee > > = > > Cherryview can have different SSEU configurations within a given PCI > > ID, so we collect the info from the fuse register. > > = > > I don't currently have access to a CHV, much less one with an interesti= ng > > fuse config. So I have compile-checked this only! > > = > > Signed-off-by: Jeff McGee > > --- > > drivers/gpu/drm/i915/Makefile | 3 +- > > drivers/gpu/drm/i915/i915_dma.c | 2 ++ > > drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++ > > drivers/gpu/drm/i915/intel_sseu.c | 64 +++++++++++++++++++++++++++++++= ++++++++ > > drivers/gpu/drm/i915/intel_sseu.h | 2 ++ > > 5 files changed, 83 insertions(+), 1 deletion(-) > > create mode 100644 drivers/gpu/drm/i915/intel_sseu.c > > = > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makef= ile > > index 91bd167..9a0f411 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -32,7 +32,8 @@ i915-y +=3D i915_cmd_parser.o \ > > i915_irq.o \ > > i915_trace_points.o \ > > intel_ringbuffer.o \ > > - intel_uncore.o > > + intel_uncore.o \ > > + intel_sseu.o > > = > > # autogenerated null render state > > i915-y +=3D intel_renderstate_gen6.o \ > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i91= 5_dma.c > > index f581848..384ef65 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -1772,6 +1772,8 @@ int i915_driver_load(struct drm_device *dev, unsi= gned long flags) > > goto out_gem_unload; > > } > > = > > + intel_sseu_init(dev); > > + > > intel_power_domains_init(dev_priv); > > = > > if (drm_core_check_feature(dev, DRIVER_MODESET)) { > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 28e21ed..24a2d56 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -5624,6 +5624,19 @@ enum punit_power_well { > > #define GEN7_MISCCPCTL (0x9424) > > #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) > > = > > +/* Fuse readout registers for GT */ > > +#define CHV_FUSE_GT 0x182168 > > +#define CHV_FUSE_GT_SUBSLICE_DISABLE_SS0 10 > > +#define CHV_FUSE_GT_SUBSLICE_DISABLE_SS1 11 > > +#define CHV_FUSE_GT_EU_DISABLE_SS0_ROW0_MASK (0xf<<16) > > +#define CHV_FUSE_GT_EU_DISABLE_SS0_ROW0_SHIFT 16 > > +#define CHV_FUSE_GT_EU_DISABLE_SS0_ROW1_MASK (0xf<<20) > > +#define CHV_FUSE_GT_EU_DISABLE_SS0_ROW1_SHIFT 20 > > +#define CHV_FUSE_GT_EU_DISABLE_SS1_ROW0_MASK (0xf<<24) > > +#define CHV_FUSE_GT_EU_DISABLE_SS1_ROW0_SHIFT 24 > > +#define CHV_FUSE_GT_EU_DISABLE_SS1_ROW1_MASK (0xf<<28) > > +#define CHV_FUSE_GT_EU_DISABLE_SS1_ROW1_SHIFT 28 > > + > > /* IVYBRIDGE DPF */ > > #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ > > #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice= 1 */ > > diff --git a/drivers/gpu/drm/i915/intel_sseu.c b/drivers/gpu/drm/i915/i= ntel_sseu.c > > new file mode 100644 > > index 0000000..6ba4830 > > --- /dev/null > > +++ b/drivers/gpu/drm/i915/intel_sseu.c > > @@ -0,0 +1,64 @@ > > +/* > > + * Copyright =A9 2014 Intel Corporation > > + * > > + * Permission is hereby granted, free of charge, to any person obtaini= ng a > > + * copy of this software and associated documentation files (the "Soft= ware"), > > + * to deal in the Software without restriction, including without limi= tation > > + * the rights to use, copy, modify, merge, publish, distribute, sublic= ense, > > + * and/or sell copies of the Software, and to permit persons to whom t= he > > + * Software is furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice (including th= e next > > + * paragraph) shall be included in all copies or substantial portions = of the > > + * Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXP= RESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABI= LITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT = SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES O= R OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARI= SING > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER= DEALINGS > > + * IN THE SOFTWARE. > > + * > > + */ > > +#include > > +#include "i915_drv.h" > > +#include "intel_sseu.h" > > + > > +void intel_sseu_init(struct drm_device *dev) > > +{ > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + struct intel_sseu_info sseu_info; > > + u32 gp =3D 0; > > + > > + /* Collect SSEU info per device */ > > + if (IS_CHERRYVIEW(dev)) { > > + u32 fuse, mask_ss, mask_eu; > > + > > + fuse =3D I915_READ(CHV_FUSE_GT); > > + mask_ss =3D fuse & (CHV_FUSE_GT_SUBSLICE_DISABLE_SS0 | > > + CHV_FUSE_GT_SUBSLICE_DISABLE_SS1); > > + mask_eu =3D fuse & (CHV_FUSE_GT_EU_DISABLE_SS0_ROW0_MASK | > > + CHV_FUSE_GT_EU_DISABLE_SS0_ROW1_MASK | > > + CHV_FUSE_GT_EU_DISABLE_SS1_ROW0_MASK | > > + CHV_FUSE_GT_EU_DISABLE_SS1_ROW1_MASK); > > + sseu_info.slice_cnt =3D 1; > > + sseu_info.subslice_cnt =3D 2 - hweight32(mask_ss); > > + sseu_info.eu_cnt =3D 16 - hweight32(mask_eu); > > + sseu_info.threads_per_eu =3D 7; > > + } > > + > > + /* Pack SSEU info bitfield for I915_PARAM_SSEU_INFO */ > > + gp |=3D (sseu_info.slice_cnt << I915_SSEU_INFO_SLICE_CNT_SHIFT) & > > + I915_SSEU_INFO_SLICE_CNT_MASK; > > + gp |=3D (sseu_info.subslice_cnt << I915_SSEU_INFO_SUBSLICE_CNT_SHIFT)= & > > + I915_SSEU_INFO_SUBSLICE_CNT_MASK; > > + gp |=3D (sseu_info.eu_cnt << I915_SSEU_INFO_EU_CNT_SHIFT) & > > + I915_SSEU_INFO_EU_CNT_MASK; > > + gp |=3D (sseu_info.threads_per_eu << I915_SSEU_INFO_THREADS_PER_EU_SH= IFT) & > > + I915_SSEU_INFO_THREADS_PER_EU_MASK; > > + sseu_info.gp_sseu_info =3D gp; > = > This leaves the question how userspace can figure out whether we actually > support this. You need to return -EINVAL or something for all platforms > where this is not yet implemented. > = Agree. I'll add that. -Jeff > > + > > + /* Copy SSEU info to the const device info with pointer magic */ > > + *(struct intel_sseu_info *)&dev_priv->info.sseu =3D sseu_info; > = > I've thought gcc just does a memcpy for plain strut assignments, i.e. > = > + dev_priv->info.sseu =3D sseu_info; > = > Cheers, Daniel > = This is necessary due to the const-ness of dev_priv->info. The straight-forward copy either fails to compile or issues a nasty warning (can't remember which right now). This same method is used in i915_driver_load to initialize dev_priv->info. -Jeff > > +} > > diff --git a/drivers/gpu/drm/i915/intel_sseu.h b/drivers/gpu/drm/i915/i= ntel_sseu.h > > index 7db7175..0257358 100644 > > --- a/drivers/gpu/drm/i915/intel_sseu.h > > +++ b/drivers/gpu/drm/i915/intel_sseu.h > > @@ -37,4 +37,6 @@ struct intel_sseu_info { > > u32 gp_sseu_info; > > }; > > = > > +extern void intel_sseu_init(struct drm_device *dev); > > + > > #endif > > -- = > > 2.0.1 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch