From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV Date: Tue, 5 Aug 2014 17:39:03 +0300 Message-ID: <20140805143903.GN4193@intel.com> References: <1405513395-7014-4-git-send-email-gajanan.bhat@intel.com> <1407261098-18467-1-git-send-email-gajanan.bhat@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C9D186E4B9 for ; Tue, 5 Aug 2014 07:39:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1407261098-18467-1-git-send-email-gajanan.bhat@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Gajanan Bhat Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 05, 2014 at 11:21:38PM +0530, Gajanan Bhat wrote: > Program DDL register as part of sprite watermark programming for CHV and = VLV. > = > v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK > = > Signed-off-by: Gajanan Bhat > --- > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 44 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 5e81c49..9126295 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1416,6 +1416,48 @@ static void valleyview_update_wm(struct drm_crtc *= crtc) > intel_set_memory_cxsr(dev_priv, true); > } > = > +static void valleyview_update_sprite_wm(struct drm_plane *plane, > + struct drm_crtc *crtc, > + uint32_t sprite_width, > + uint32_t sprite_height, > + int pixel_size, > + bool enabled, bool scaled) > +{ > + struct drm_device *dev =3D crtc->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + int pipe =3D to_intel_plane(plane)->pipe; > + int drain_latency; > + int plane_prec; > + int sprite_dl; > + int prec_mult; > + > + if (to_intel_plane(plane)->plane =3D=3D 0) > + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE0_PRECISION_64 & > + ~(DRAIN_LATENCY_MASK << DDL_SPRITE0_SHIFT); > + else > + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE1_PRECISION_64 & > + ~(DRAIN_LATENCY_MASK << DDL_SPRITE1_SHIFT); I was thinking we migth want to parametrize the DDL_SPRITE bits to avoid these if-else things. So something like this: #define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite))) #define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite))) #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) Also you should again use the more customary form for masking the bits: I915_READ() & ~(DDL_SPRITE_PRECISION_64 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT)); > + > + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, > + &drain_latency)) { > + if (to_intel_plane(plane)->plane =3D=3D 0) { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_SPRITE0_PRECISION_64 : > + DDL_SPRITE0_PRECISION_32; > + sprite_dl =3D sprite_dl | plane_prec | > + drain_latency << DDL_SPRITE0_SHIFT; > + } else { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_SPRITE1_PRECISION_64 : > + DDL_SPRITE1_PRECISION_32; > + sprite_dl =3D sprite_dl | plane_prec | > + drain_latency << DDL_SPRITE1_SHIFT; > + } > + } > + > + I915_WRITE(VLV_DDL(pipe), sprite_dl); > +} > + > static void g4x_update_wm(struct drm_crtc *crtc) > { > struct drm_device *dev =3D crtc->dev; > @@ -7134,10 +7176,12 @@ void intel_init_pm(struct drm_device *dev) > dev_priv->display.init_clock_gating =3D gen8_init_clock_gating; > } else if (IS_CHERRYVIEW(dev)) { > dev_priv->display.update_wm =3D valleyview_update_wm; > + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating =3D > cherryview_init_clock_gating; > } else if (IS_VALLEYVIEW(dev)) { > dev_priv->display.update_wm =3D valleyview_update_wm; > + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating =3D > valleyview_init_clock_gating; > } else if (IS_PINEVIEW(dev)) { > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC