From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 05/15] drm/i915: Don't promote UC to WT automagically Date: Wed, 6 Aug 2014 09:57:39 +0200 Message-ID: <20140806075739.GR8727@phenom.ffwll.local> References: <1407250286-1801-1-git-send-email-rodrigo.vivi@intel.com> <1407250286-1801-6-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f47.google.com (mail-wg0-f47.google.com [74.125.82.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EA6689DB7 for ; Wed, 6 Aug 2014 00:57:27 -0700 (PDT) Received: by mail-wg0-f47.google.com with SMTP id b13so2218280wgh.30 for ; Wed, 06 Aug 2014 00:57:26 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1407250286-1801-6-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 05, 2014 at 07:51:16AM -0700, Rodrigo Vivi wrote: > From: Ville Syrj=E4l=E4 > = > If the object is already UC leave it as UC instead of automagically > promoting it to WT in i915_gem_object_pin_to_display_plane() when > the hardware is WT capable. > = > Supposedly the user wanted UC for a reason, so let's respect that. > = > Signed-off-by: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi We don't have a use case for this, so can be dropped. -Daniel > --- > drivers/gpu/drm/i915/i915_gem.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_= gem.c > index dcd8d7b..5710571 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3840,6 +3840,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i91= 5_gem_object *obj, > struct intel_engine_cs *pipelined) > { > u32 old_read_domains, old_write_domain; > + unsigned int cache_level; > bool was_pin_display; > int ret; > = > @@ -3864,8 +3865,12 @@ i915_gem_object_pin_to_display_plane(struct drm_i9= 15_gem_object *obj, > * of uncaching, which would allow us to flush all the LLC-cached data > * with that bit in the PTE to main memory with just one PIPE_CONTROL. > */ > - ret =3D i915_gem_object_set_cache_level(obj, > - HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); > + if (HAS_WT(obj->base.dev) && obj->cache_level !=3D I915_CACHE_NONE) > + cache_level =3D I915_CACHE_WT; > + else > + cache_level =3D I915_CACHE_NONE; > + > + ret =3D i915_gem_object_set_cache_level(obj, cache_level); > if (ret) > goto err_unpin_display; > = > -- = > 1.9.3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch