From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v3] drm/i915: Generalize drain latency computation Date: Wed, 6 Aug 2014 21:49:02 +0200 Message-ID: <20140806194902.GT8727@phenom.ffwll.local> References: <20140805125615.GK4193@intel.com> <1407356904-21201-1-git-send-email-gajanan.bhat@intel.com> <20140806150712.GW4193@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f169.google.com (mail-we0-f169.google.com [74.125.82.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 372B86E1DC for ; Wed, 6 Aug 2014 12:48:51 -0700 (PDT) Received: by mail-we0-f169.google.com with SMTP id u56so3156603wes.28 for ; Wed, 06 Aug 2014 12:48:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140806150712.GW4193@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Aug 06, 2014 at 06:07:12PM +0300, Ville Syrj=E4l=E4 wrote: > On Thu, Aug 07, 2014 at 01:58:24AM +0530, Gajanan Bhat wrote: > > Modify drain latency computation to use it for any plane. Same function= can be > > used for primary, cursor and sprite planes. > > = > > v2: Adressed review comments by Imre and Ville. > > - Moved clock round up in separate patch > > - Added WARN check for clock and pixel size > > - Simplified bit masking > > - Use cursor_base instead of reg read > > = > > v3: Changed to bitwise shorthand operator for plane_dl assignment. > > = > > Signed-off-by: Gajanan Bhat > = > Reviewed-by: Ville Syrj=E4l=E4 Pulled in these two patches. -Danil > = > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 87 ++++++++++++++++++++++---------= -------- > > 2 files changed, 51 insertions(+), 37 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 187f862..08916df 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4009,6 +4009,7 @@ enum punit_power_well { > > #define DDL_PLANE_PRECISION_64 (1<<7) > > #define DDL_PLANE_PRECISION_32 (0<<7) > > #define DDL_PLANE_SHIFT 0 > > +#define DRAIN_LATENCY_MASK 0x7f > > = > > /* FIFO watermark sizes etc */ > > #define G4X_FIFO_LINE_SIZE 64 > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index ba8dfeb..cabea4b 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -1277,33 +1277,24 @@ static bool g4x_compute_srwm(struct drm_device = *dev, > > display, cursor); > > } > > = > > -static bool vlv_compute_drain_latency(struct drm_device *dev, > > - int plane, > > - int *plane_prec_mult, > > - int *plane_dl, > > - int *cursor_prec_mult, > > - int *cursor_dl) > > +static bool vlv_compute_drain_latency(struct drm_crtc *crtc, > > + int pixel_size, > > + int *prec_mult, > > + int *drain_latency) > > { > > - struct drm_crtc *crtc; > > - int clock, pixel_size; > > int entries; > > + int clock =3D to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; > > = > > - crtc =3D intel_get_crtc_for_plane(dev, plane); > > - if (!intel_crtc_active(crtc)) > > + if (WARN(clock =3D=3D 0, "Pixel clock is zero!\n")) > > return false; > > = > > - clock =3D to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; > > - pixel_size =3D crtc->primary->fb->bits_per_pixel / 8; /* BPP */ > > + if (WARN(pixel_size =3D=3D 0, "Pixel size is zero!\n")) > > + return false; > > = > > entries =3D (clock / 1000) * pixel_size; > > - *plane_prec_mult =3D (entries > 128) ? > > - DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > > - *plane_dl =3D (64 * (*plane_prec_mult) * 4) / entries; > > - > > - entries =3D (clock / 1000) * 4; /* BPP is always 4 for cursor */ > > - *cursor_prec_mult =3D (entries > 128) ? > > - DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > > - *cursor_dl =3D (64 * (*cursor_prec_mult) * 4) / entries; > > + *prec_mult =3D (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : > > + DRAIN_LATENCY_PRECISION_32; > > + *drain_latency =3D (64 * (*prec_mult) * 4) / entries; > > = > > return true; > > } > > @@ -1318,24 +1309,46 @@ static bool vlv_compute_drain_latency(struct dr= m_device *dev, > > = > > static void vlv_update_drain_latency(struct drm_crtc *crtc) > > { > > - struct drm_device *dev =3D crtc->dev; > > - struct drm_i915_private *dev_priv =3D dev->dev_private; > > - enum pipe pipe =3D to_intel_crtc(crtc)->pipe; > > - int plane_prec, plane_dl; > > - int cursor_prec, cursor_dl; > > - int plane_prec_mult, cursor_prec_mult; > > - > > - if (vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl, > > - &cursor_prec_mult, &cursor_dl)) { > > - cursor_prec =3D (cursor_prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64)= ? > > - DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32; > > - plane_prec =3D (plane_prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > > - DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32; > > - > > - I915_WRITE(VLV_DDL(pipe), cursor_prec | > > - (cursor_dl << DDL_CURSOR_SHIFT) | > > - plane_prec | (plane_dl << DDL_PLANE_SHIFT)); > > + struct drm_i915_private *dev_priv =3D crtc->dev->dev_private; > > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > + int pixel_size; > > + int drain_latency; > > + enum pipe pipe =3D intel_crtc->pipe; > > + int plane_prec, prec_mult, plane_dl; > > + > > + plane_dl =3D I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 | > > + DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 | > > + (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); > > + > > + if (!intel_crtc_active(crtc)) { > > + I915_WRITE(VLV_DDL(pipe), plane_dl); > > + return; > > + } > > + > > + /* Primary plane Drain Latency */ > > + pixel_size =3D crtc->primary->fb->bits_per_pixel / 8; /* BPP */ > > + if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_la= tency)) { > > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > > + DDL_PLANE_PRECISION_64 : > > + DDL_PLANE_PRECISION_32; > > + plane_dl |=3D plane_prec | drain_latency; > > } > > + > > + /* Cursor Drain Latency > > + * BPP is always 4 for cursor > > + */ > > + pixel_size =3D 4; > > + > > + /* Program cursor DL only if it is enabled */ > > + if (intel_crtc->cursor_base && > > + vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_la= tency)) { > > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > > + DDL_CURSOR_PRECISION_64 : > > + DDL_CURSOR_PRECISION_32; > > + plane_dl |=3D plane_prec | (drain_latency << DDL_CURSOR_SHIFT); > > + } > > + > > + I915_WRITE(VLV_DDL(pipe), plane_dl); > > } > > = > > #define single_plane_enabled(mask) is_power_of_2(mask) > > -- = > > 1.7.9.5 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch