From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Continuation of future readiness series Date: Fri, 8 Aug 2014 16:15:21 +0200 Message-ID: <20140808141521.GV8727@phenom.ffwll.local> References: <1407497954-25230-1-git-send-email-sonika.jindal@intel.com> <20140808115510.GE4193@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f52.google.com (mail-wg0-f52.google.com [74.125.82.52]) by gabe.freedesktop.org (Postfix) with ESMTP id AC0F36E11D for ; Fri, 8 Aug 2014 07:15:09 -0700 (PDT) Received: by mail-wg0-f52.google.com with SMTP id a1so5601033wgh.35 for ; Fri, 08 Aug 2014 07:15:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140808115510.GE4193@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 08, 2014 at 02:55:10PM +0300, Ville Syrj=E4l=E4 wrote: > On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jindal@intel.com wrote: > > From: Sonika Jindal > > = > > Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways = all the > > platforms are checked separately. > > = > > Signed-off-by: Sonika Jindal > > --- > > drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++----------= -------- > > 1 file changed, 19 insertions(+), 21 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 89e0ac5..5a3e239 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_dev= ice *dev) > > dev_priv->display.get_display_clock_speed =3D > > i830_get_display_clock_speed; > > = > > - if (HAS_PCH_SPLIT(dev)) { > > - if (IS_GEN5(dev)) { > > - dev_priv->display.fdi_link_train =3D ironlake_fdi_link_train; > > - dev_priv->display.write_eld =3D ironlake_write_eld; > > - } else if (IS_GEN6(dev)) { > > - dev_priv->display.fdi_link_train =3D gen6_fdi_link_train; > > - dev_priv->display.write_eld =3D ironlake_write_eld; > > - dev_priv->display.modeset_global_resources =3D > > - snb_modeset_global_resources; > > - } else if (IS_IVYBRIDGE(dev)) { > > - /* FIXME: detect B0+ stepping and use auto training */ > > - dev_priv->display.fdi_link_train =3D ivb_manual_fdi_link_train; > > - dev_priv->display.write_eld =3D ironlake_write_eld; > > - dev_priv->display.modeset_global_resources =3D > > - ivb_modeset_global_resources; > > - } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { > > - dev_priv->display.fdi_link_train =3D hsw_fdi_link_train; > > - dev_priv->display.write_eld =3D haswell_write_eld; > > - dev_priv->display.modeset_global_resources =3D > > - haswell_modeset_global_resources; > > - } > > + if (IS_GEN5(dev)) { > > + dev_priv->display.fdi_link_train =3D ironlake_fdi_link_train; > > + dev_priv->display.write_eld =3D ironlake_write_eld; > > + } else if (IS_GEN6(dev)) { > > + dev_priv->display.fdi_link_train =3D gen6_fdi_link_train; > > + dev_priv->display.write_eld =3D ironlake_write_eld; > > + dev_priv->display.modeset_global_resources =3D > > + snb_modeset_global_resources; > > + } else if (IS_IVYBRIDGE(dev)) { > > + /* FIXME: detect B0+ stepping and use auto training */ > > + dev_priv->display.fdi_link_train =3D ivb_manual_fdi_link_train; > > + dev_priv->display.write_eld =3D ironlake_write_eld; > > + dev_priv->display.modeset_global_resources =3D > > + ivb_modeset_global_resources; > > + } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { > > + dev_priv->display.fdi_link_train =3D hsw_fdi_link_train; > > + dev_priv->display.write_eld =3D haswell_write_eld; > > + dev_priv->display.modeset_global_resources =3D > > + haswell_modeset_global_resources; > = > Maybe shuffle these around a bit while you're at it so that the checks > would be roughly in gen order. Agreed, that might be useful while we touch the code. There's no preference over newer-first or older-first ordering, so you can pick what you like. G4X =3D gen4.5, so oldest platform that supports DP. -Daniel > = > > } else if (IS_G4X(dev)) { > > dev_priv->display.write_eld =3D g4x_write_eld; > > } else if (IS_VALLEYVIEW(dev)) { > > -- = > > 1.7.10.4 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch