From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 17/43] drm/i915/bdw: GEN-specific logical ring set/get seqno Date: Mon, 11 Aug 2014 17:05:25 +0200 Message-ID: <20140811150525.GP10500@phenom.ffwll.local> References: <1406217891-8912-1-git-send-email-thomas.daniel@intel.com> <1406217891-8912-18-git-send-email-thomas.daniel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f45.google.com (mail-wg0-f45.google.com [74.125.82.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B6A86E3FE for ; Mon, 11 Aug 2014 08:05:13 -0700 (PDT) Received: by mail-wg0-f45.google.com with SMTP id x12so8769988wgg.16 for ; Mon, 11 Aug 2014 08:05:12 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406217891-8912-18-git-send-email-thomas.daniel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Thomas Daniel Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 24, 2014 at 05:04:25PM +0100, Thomas Daniel wrote: > From: Oscar Mateo > > No mistery here: the seqno is still retrieved from the engine's > HW status page (the one in the default context. For the moment, > I see no reason to worry about other context's HWS page). > > Signed-off-by: Oscar Mateo Ok, merged or bikeshedded up to this one. I need a bit a break to recharge, will continue later on. Cheers, Daniel > --- > drivers/gpu/drm/i915/intel_lrc.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 7c8b75e..f171fd5 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -149,6 +149,16 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring) > return ret; > } > > +static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) > +{ > + return intel_read_status_page(ring, I915_GEM_HWS_INDEX); > +} > + > +static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) > +{ > + intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); > +} > + > void intel_logical_ring_cleanup(struct intel_engine_cs *ring) > { > if (!intel_ring_initialized(ring)) > @@ -221,6 +231,8 @@ static int logical_render_ring_init(struct drm_device *dev) > > ring->init = gen8_init_render_ring; > ring->cleanup = intel_fini_pipe_control; > + ring->get_seqno = gen8_get_seqno; > + ring->set_seqno = gen8_set_seqno; > > return logical_ring_init(dev, ring); > } > @@ -237,6 +249,8 @@ static int logical_bsd_ring_init(struct drm_device *dev) > GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; > > ring->init = gen8_init_common_ring; > + ring->get_seqno = gen8_get_seqno; > + ring->set_seqno = gen8_set_seqno; > > return logical_ring_init(dev, ring); > } > @@ -253,6 +267,8 @@ static int logical_bsd2_ring_init(struct drm_device *dev) > GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; > > ring->init = gen8_init_common_ring; > + ring->get_seqno = gen8_get_seqno; > + ring->set_seqno = gen8_set_seqno; > > return logical_ring_init(dev, ring); > } > @@ -269,6 +285,8 @@ static int logical_blt_ring_init(struct drm_device *dev) > GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; > > ring->init = gen8_init_common_ring; > + ring->get_seqno = gen8_get_seqno; > + ring->set_seqno = gen8_set_seqno; > > return logical_ring_init(dev, ring); > } > @@ -285,6 +303,8 @@ static int logical_vebox_ring_init(struct drm_device *dev) > GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; > > ring->init = gen8_init_common_ring; > + ring->get_seqno = gen8_get_seqno; > + ring->set_seqno = gen8_set_seqno; > > return logical_ring_init(dev, ring); > } > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch