From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2] drm/i915: Don't warn if we restore pm interrupts during reset Date: Thu, 14 Aug 2014 17:45:59 +0300 Message-ID: <20140814144559.GE4193@intel.com> References: <1408019794-12982-1-git-send-email-mika.kuoppala@intel.com> <1408020403-21956-1-git-send-email-mika.kuoppala@intel.com> <20140814142316.GP10500@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 933DA6E266 for ; Thu, 14 Aug 2014 07:46:03 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140814142316.GP10500@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Aug 14, 2014 at 04:23:16PM +0200, Daniel Vetter wrote: > On Thu, Aug 14, 2014 at 03:46:43PM +0300, Mika Kuoppala wrote: > > We lost the software state tracking due to reset, so don't > > complain if it doesn't match. > = > This sounds more like gpu reset should be a bit more careful (even more > careful than we already are compared to earlier kernels) with making sure > the irq state is still sane after a reset? > = > Or what exactly is the failure mode here? The commit message lacks a bit > details in form of a nice text or even better: A testcase ;-) Killing the hpd irq and gt_powersave junk from i915_reset() would be my suggestion here. I don't even know why the hpd stuff is still there, we removed all the other irq frobbery from there a while back. And last I looked gpu reset didn't affect the rc6/rps stuff either, though more testing should be done to make sure I didn't just imagine it. > = > Thanks, Daniel > = > > = > > v2: fix build error > > = > > Signed-off-by: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 12f4e14..7a1309c 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3593,7 +3593,8 @@ static void gen8_enable_rps_interrupts(struct drm= _device *dev) > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > = > > spin_lock_irq(&dev_priv->irq_lock); > > - WARN_ON(dev_priv->rps.pm_iir); > > + if (!i915_reset_in_progress(&dev_priv->gpu_error)) > > + WARN_ON(dev_priv->rps.pm_iir); > > gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > > I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); > > spin_unlock_irq(&dev_priv->irq_lock); > > @@ -3604,7 +3605,8 @@ static void gen6_enable_rps_interrupts(struct drm= _device *dev) > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > = > > spin_lock_irq(&dev_priv->irq_lock); > > - WARN_ON(dev_priv->rps.pm_iir); > > + if (!i915_reset_in_progress(&dev_priv->gpu_error)) > > + WARN_ON(dev_priv->rps.pm_iir); > > gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > > I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); > > spin_unlock_irq(&dev_priv->irq_lock); > > -- = > > 1.7.9.5 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC