From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v2] drm/i915: Fix to Enable GT/PM Interrupts
 for cherryview.
Date: Thu, 21 Aug 2014 10:54:21 +0300
Message-ID: <20140821075421.GJ4193@intel.com>
References: <20140820105616.GE4193@intel.com>
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On Fri, Aug 22, 2014 at 08:32:40AM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> =

> Programing GT IER interrupts was fumbled while enabling Interrupts for
> gen8
> =

> This is a regression from
>     commit abd58f0175915bed644aa67c8f69dc571b8280e0
>     Author: Ben Widawsky <benjamin.widawsky@intel.com>
>     Date:   Sat Nov 2 21:07:09 2013 -0700
> =

> 	drm/i915/bdw: Implement interrupt changes
> =

> v2: Kill the loop and init GT interrupts (Ville)
> =

> Signed-off-by: Deepak S <deepak.s@linux.intel.com>

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> =

> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_=
irq.c
> index d5445e7..c33cf89 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3799,8 +3799,6 @@ static int valleyview_irq_postinstall(struct drm_de=
vice *dev)
>  =

>  static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -	int i;
> -
>  	/* These are interrupts we'll toggle with the ring mask register */
>  	uint32_t gt_interrupts[] =3D {
>  		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> @@ -3817,10 +3815,11 @@ static void gen8_gt_irq_postinstall(struct drm_i9=
15_private *dev_priv)
>  			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
>  		};
>  =

> -	for (i =3D 0; i < ARRAY_SIZE(gt_interrupts); i++)
> -		GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
> -
>  	dev_priv->pm_irq_mask =3D 0xffffffff;
> +	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
> +	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
> +	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events=
);
> +	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
>  }
>  =

>  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> -- =

> 1.9.1

-- =

Ville Syrj=E4l=E4
Intel OTC