From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 4/4] drm/i915/bdw: Map unused PDPs to a
 scratch page
Date: Tue, 26 Aug 2014 10:05:40 +0200
Message-ID: <20140826080540.GD15520@phenom.ffwll.local>
References: <1408383330-21935-1-git-send-email-rodrigo.vivi@intel.com>
 <1408383330-21935-5-git-send-email-rodrigo.vivi@intel.com>
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To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>, intel-gfx@lists.freedesktop.org
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On Mon, Aug 18, 2014 at 10:35:30AM -0700, Rodrigo Vivi wrote:
> From: Bob Beckett <robert.beckett@intel.com>
> 
> Create a scratch page for the two unused PDPs and set all the PTEs
> for them to point to it.
> 
> This patch addresses a page fault, and subsequent hang in pipe
> control flush. In these cases, the Main Graphic Arbiter Error
> register [0x40A0] showed a TLB Page Fault error, and a high memory
> address (higher than the size of our PPGTT) was reported in the
> Fault TLB RD Data0 register (0x4B10).
> 
> PDP2 & PDP3 were not set because, in theory, they aren't required
> for our PPGTT size, but they should be mapped to a scratch page
> anyway.
> 
> v2: Rebase on latest nightly.
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v1)
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com> (v2)
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

No idea about this one, especially since there's tons of other bdw ppgtt
patches in-flight. I've merged all the others though.

Aside: We need to figure out how to make people review their -collector
assignments actually, it seems to totally not work :(
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch