From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 11/16] drm/i915: Init important ns2501 registers Date: Mon, 1 Sep 2014 10:42:05 +0200 Message-ID: <20140901084205.GS15520@phenom.ffwll.local> References: <1408054928-24141-1-git-send-email-ville.syrjala@linux.intel.com> <1408054928-24141-12-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by gabe.freedesktop.org (Postfix) with ESMTP id A97E489EB1 for ; Mon, 1 Sep 2014 01:41:42 -0700 (PDT) Received: by mail-we0-f178.google.com with SMTP id u57so5104111wes.9 for ; Mon, 01 Sep 2014 01:41:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1408054928-24141-12-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: Thomas Richter , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 15, 2014 at 01:22:03AM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > In my earlier rewrite I missed a few important registers. Thomas Richter > noticed that they're needed to make his machine resume correctly. > = > Looks like IEGD does a one time init of these three registers. We don't > have a good one time init place in the ns2501 driver, so let's just > stick them into the .mode_set() hook and see if that helps things along. We have the encoder->reset hooks which are commonly used for such stuff. Not worth to wire that up for dvo, just an fyi really. -Daniel > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/dvo_ns2501.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo= _ns2501.c > index b278571..345235b 100644 > --- a/drivers/gpu/drm/i915/dvo_ns2501.c > +++ b/drivers/gpu/drm/i915/dvo_ns2501.c > @@ -342,6 +342,12 @@ static const struct ns2501_reg regs_1024x768[][86] = =3D { > }, > }; > = > +static const struct ns2501_reg regs_init[] =3D { > + [0] =3D { .offset =3D 0x35, .value =3D 0xff, }, > + [1] =3D { .offset =3D 0x34, .value =3D 0x00, }, > + [2] =3D { .offset =3D 0x08, .value =3D 0x30, }, > +}; > + > struct ns2501_priv { > bool quiet; > const struct ns2501_reg *regs; > @@ -544,6 +550,10 @@ static void ns2501_mode_set(struct intel_dvo_device = *dvo, > else > return; > = > + /* Hopefully doing it every time won't hurt... */ > + for (i =3D 0; i < ARRAY_SIZE(regs_init); i++) > + ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value); > + > ns->regs =3D regs_1024x768[mode_idx]; > = > for (i =3D 0; i < 84; i++) > -- = > 1.8.5.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch