From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: WARN if interrupts aren't on in
 en/disable_pipestat
Date: Mon, 8 Sep 2014 10:18:12 +0200
Message-ID: <20140908081812.GU15520@phenom.ffwll.local>
References: <1409129017-16857-1-git-send-email-daniel.vetter@ffwll.ch>
 <20140827160022.2a8fe834@jbarnes-desktop>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mail-wg0-f44.google.com (mail-wg0-f44.google.com [74.125.82.44])
 by gabe.freedesktop.org (Postfix) with ESMTP id 41FE46E216
 for <intel-gfx@lists.freedesktop.org>; Mon,  8 Sep 2014 01:17:47 -0700 (PDT)
Received: by mail-wg0-f44.google.com with SMTP id y10so702586wgg.3
 for <intel-gfx@lists.freedesktop.org>; Mon, 08 Sep 2014 01:17:46 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140827160022.2a8fe834@jbarnes-desktop>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Wed, Aug 27, 2014 at 04:00:22PM -0700, Jesse Barnes wrote:
> On Wed, 27 Aug 2014 10:43:37 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > Now that vlv has runtime pm we kinda should check for that like on the
> > pch split platforms. Looks like this was simply lost in the vlv rpm
> > enabling.
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 9eb303c1b621..76bc4d0de5a4 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -589,6 +589,7 @@ __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
> >  	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
> >  
> >  	assert_spin_locked(&dev_priv->irq_lock);
> > +	WARN_ON(!intel_irqs_enabled(dev_priv));
> >  
> >  	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> >  		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
> > @@ -615,6 +616,7 @@ __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
> >  	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
> >  
> >  	assert_spin_locked(&dev_priv->irq_lock);
> > +	WARN_ON(!intel_irqs_enabled(dev_priv));
> >  
> >  	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> >  		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
> 
> Yeah looks good, wonder if it'll trigger any new warnings.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Since Jani just merged the driver load ordering patch I've pulled this one
into dinq to maximise testing coverage. Let's see what happens ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch