From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: HSW always use GGTT selector for
 secure batches
Date: Wed, 10 Sep 2014 14:16:32 +0200
Message-ID: <20140910121632.GR15520@phenom.ffwll.local>
References: <20140910103045.GQ4193@intel.com>
 <1410347907-1020-1-git-send-email-chris@chris-wilson.co.uk>
 <20140910112143.GB31074@nuc-i3427.alporthouse.com>
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To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Wed, Sep 10, 2014 at 03:00:03PM +0300, Ville Syrj=E4l=E4 wrote:
> On Wed, Sep 10, 2014 at 12:21:43PM +0100, Chris Wilson wrote:
> > On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote:
> > > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> > > the security bit (i.e. only privileged batches were allowed to run fr=
om
> > > ggtt). From Haswell onwards, you are able to select the security bit
> > =

> > ggtt). For Haswell only, you are able to select the security bit

Rectified.

> > > separate from the address space - and we always requested to use ppgt=
t.
> > > This breaks the golden render state batch execution with full-ppgtt as
> > > that is only present in the global GTT and more generally any secure
> > > batch that is not colocated in the ppgtt and ggtt. So we need to
> > > disable the use of the ppgtt selector bit for secure batches, or else=
 we
> > > hang immediately upon boot and thence after every GPU reset...
> > > =

> > > v2: Only HSW differentiates between secure dispatch and ggtt, so simp=
ly
> > > ignore the differentiation and always use secure=3D=3Dggtt.
> > > =

> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch