From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: GPU-hang on i830 Date: Wed, 10 Sep 2014 17:00:01 +0300 Message-ID: <20140910140001.GT4193@intel.com> References: <5410415A.2010405@math.tu-berlin.de> <23616_1410351737_54104279_23616_5929_1_20140910122240.GT15520@phenom.ffwll.local> <5410514B.2030207@math.tu-berlin.de> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 3783789E0E for ; Wed, 10 Sep 2014 07:00:07 -0700 (PDT) Content-Disposition: inline In-Reply-To: <5410514B.2030207@math.tu-berlin.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Thomas Richter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Wed, Sep 10, 2014 at 03:25:31PM +0200, Thomas Richter wrote: > Am 10.09.2014 14:22, schrieb Daniel Vetter: > > On Wed, Sep 10, 2014 at 02:17:30PM +0200, Thomas Richter wrote: > >> Hi Daniel, hi Ville, > >> > >> just tried the new 3.17.0+rc4 kernel, though with old userspace (i.e. > >> xserver-xorg-video-intel is *old*, libdrm is old, mesa is old). If I d= o, I > >> get a "GPU hung" from xorg.conf. The same userspace works fine on 3.15= .0 > >> with patches from Ville. > >> > >> Is this expected behavior or should I open up a bug report (I have dme= sg > >> output and debugging output from DRI ready on this, but it's a bith > >> lengthy.) > > Please retest with latest drm-intel-nightly, if just merged a patch from > > Chris to prevent gpu hangs on i830/i845. If it still blows up please > > attach and error state captured from that kernel. > No, not merged from a patch. This is a clean checkout of "master". = > drm-intel-nightly did not contain the watermark fixes > the last time I checked. Error state is attached. I put Chris into CC. The w/a batch is corrupted. 0x400-0x1000 somehow got turned into zeroes. Both are page boundaries, so I guess trying out Chris's TLB fix would be worth a shot. This is the commit you want: commit c4d69da167fa967749aeb70bc0e94a457e5d00c1 Author: Chris Wilson Date: Mon Sep 8 14:25:41 2014 +0100 drm/i915: Evict CS TLBs between batches I just trawled through BSpec a bit and I see a clear note there that BLT TLBs are hosed on 830/845 and we need to flush after touching PTEs so that BLT will see the correct stuff. There's also a note that touching PGETBL_CTL enable bit would also flush all TLBs. So I wonder if just I915_WRITE(PGETBL_CTL, I915_READ(PGETBL_CTL)) after touching the PTEs would be enough to eliminate this problem? -- = Ville Syrj=E4l=E4 Intel OTC