From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Clear PCODE_DATA1 on SNB+ Date: Wed, 10 Sep 2014 20:32:28 +0300 Message-ID: <20140910173228.GZ4193@intel.com> References: <1409921592-23754-1-git-send-email-damien.lespiau@intel.com> <1409921592-23754-3-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 8901E6E391 for ; Wed, 10 Sep 2014 10:32:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1409921592-23754-3-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 05, 2014 at 01:53:12PM +0100, Damien Lespiau wrote: > Ville found out that the DATA1 register exists since SNB with some > scarce apparitions in the specs throughout the times. In his own words: > = > Also according to Bspec the mailbox data1 register already existed > since snb. The hsw cdclk change sequence also mentions that it should > be set to 0, but eg. the bdw IPS sequence doesn't mention it. I guess > in theory some pcode command might cause it to be clobbered, so I'm > thinking we should just explicitly set it to 0 for all platforms in > the pcode read/write functions > = > Suggested-by: Ville Syrj=E4l=E4 > Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 3 +-- > 2 files changed, 2 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 5a7adb1..56cccde 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5952,8 +5952,8 @@ enum skl_disp_power_wells { > #define GEN6_PCODE_DATA 0x138128 > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > +#define GEN6_PCODE_DATA1 0x13812C > = > -#define GEN9_PCODE_DATA1 0x13812C > #define GEN9_PCODE_READ_MEM_LATENCY 0x6 > #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 3f69f9a..7bc8f73 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -8716,8 +8716,7 @@ int sandybridge_pcode_read(struct drm_i915_private = *dev_priv, u8 mbox, u32 *val) > } > = > I915_WRITE(GEN6_PCODE_DATA, *val); > - if (INTEL_INFO(dev_priv)->gen >=3D 9) > - I915_WRITE(GEN9_PCODE_DATA1, 0); > + I915_WRITE(GEN6_PCODE_DATA1, 0); > I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); > = > if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) =3D=3D = 0, > -- = > 1.8.3.1 -- = Ville Syrj=E4l=E4 Intel OTC