From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v2] drm/i915: Don't enable IPS when pixel
 rate exceeds 95% of cdclk
Date: Fri, 12 Sep 2014 18:49:42 +0300
Message-ID: <20140912154942.GD12416@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Sep 12, 2014 at 04:42:33PM +0100, Chris Wilson wrote:
> On Fri, Sep 12, 2014 at 05:01:57PM +0300, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
> > exceeds 95% of the core display clock. Apparently this can cause
> > underruns.
> > =

> > There's no similar restriction listed for HSW, so leave that one alone
> > for now.
> > =

> > v2: Add pipe_config_supports_ips() (Chris)
> > =

> > Tested-by: Timo Aaltonen <tjaalton@ubuntu.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D83497
> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++++++--
> >  drivers/gpu/drm/i915/intel_drv.h     |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c      | 16 +++++++---------
> >  3 files changed, 27 insertions(+), 11 deletions(-)
> > =

> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91=
5/intel_display.c
> > index 965eb3c..7809177 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5241,12 +5241,29 @@ retry:
> >  	return setup_ok ? 0 : -EINVAL;
> >  }
> >  =

> > +static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
> > +				     struct intel_crtc_config *pipe_config)
> > +{
> > +	if (pipe_config->pipe_bpp > 24)
> > +		return false;
> > +
> > +	/* HSW can handle pixel rate up to cdclk? */
> > +	if (IS_HASWELL(dev_priv->dev))
> =

> This only needs IS_HASWELL(dev_priv)

old habits...

> =

> > +		return true;
> > +
> > +	return ilk_pipe_pixel_rate(pipe_config) <=3D
> > +		intel_ddi_get_cdclk_freq(dev_priv) * 95 / 100;
> =

> Otherwise
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
> =

> -- =

> Chris Wilson, Intel Open Source Technology Centre

-- =

Ville Syrj=E4l=E4
Intel OTC