From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 79/89] drm/i915/skl: Read back the DDB allocation hw state Date: Fri, 19 Sep 2014 13:54:56 +0300 Message-ID: <20140919105456.GJ12416@intel.com> References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com> <1409830075-11139-80-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 53C3F89DE3 for ; Fri, 19 Sep 2014 03:55:02 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1409830075-11139-80-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Sep 04, 2014 at 12:27:45PM +0100, Damien Lespiau wrote: > This logically belongs to the WM state, so do it there. > = > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index d378879..8d24a4d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3020,6 +3020,32 @@ static unsigned int skl_cursor_allocation(struct i= ntel_wm_config *config) > return 8; > } > = > +static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 = reg) > +{ > + entry->start =3D reg & 0x3ff; > + entry->end =3D (reg >> 16) & 0x3ff; Would need a rebase in case the HW register is really inclusive and we make skl_ddb_entry.end exclusive. Apart from that = Reviewed-by: Ville Syrj=E4l=E4 > +} > + > +static void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > + struct skl_ddb_allocation *ddb /* out */) > +{ > + struct drm_device *dev =3D dev_priv->dev; > + enum pipe pipe; > + int plane; > + u32 val; > + > + for_each_pipe(dev_priv, pipe) { > + for_each_plane(pipe, plane) { > + val =3D I915_READ(PLANE_BUF_CFG(pipe, plane)); > + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], > + val); > + } > + > + val =3D I915_READ(CUR_BUF_CFG(pipe)); > + skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); > + } > +} > + > static unsigned int > skl_plane_relative_data_rate(struct intel_plane_wm_parameters *p) > { > @@ -3810,8 +3836,11 @@ static void skl_pipe_wm_get_hw_state(struct drm_cr= tc *crtc) > = > void skl_wm_get_hw_state(struct drm_device *dev) > { > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct skl_ddb_allocation *ddb =3D &dev_priv->wm.skl_hw.ddb; > struct drm_crtc *crtc; > = > + skl_ddb_get_hw_state(dev_priv, ddb); > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) > skl_pipe_wm_get_hw_state(crtc); > } > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC