From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/bdw: Cleanup pre prod workarounds
Date: Fri, 19 Sep 2014 16:55:56 +0300 [thread overview]
Message-ID: <20140919135556.GN12416@intel.com> (raw)
In-Reply-To: <1411131908-29771-1-git-send-email-mika.kuoppala@intel.com>
On Fri, Sep 19, 2014 at 04:05:08PM +0300, Mika Kuoppala wrote:
> as these have been fixed in production hw and hurt performance
> if applied.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482
> Tested-by: zhoujian <jianx.zhou@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 681ea86..dfb3bc6 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>
> - /*
> - * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
> - * pre-production hardware
> - */
> intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
> - _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
> - | GEN8_SAMPLER_POWER_BYPASS_DIS));
> -
> - intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
> - _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
> -
> - intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
> - _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
> + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
You should adjust the requested ring space too. Looks like this will
leave the number of intel_ring_emit_wa() calls even so no need to
worry about the QW tail padding quite yet.
>
> /* Use Force Non-Coherent whenever executing a 3D context. This is a
> * workaround for for a possible hang in the unlikely event a TLB
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-09-19 13:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-19 13:05 [PATCH] drm/i915/bdw: Cleanup pre prod workarounds Mika Kuoppala
2014-09-19 13:55 ` Ville Syrjälä [this message]
2014-09-19 17:05 ` Mika Kuoppala
2014-09-19 17:49 ` Ville Syrjälä
2014-09-23 8:20 ` Daniel Vetter
2014-09-23 11:48 ` Jani Nikula
2014-09-24 8:41 ` Daniel Vetter
2014-09-24 17:46 ` Rodrigo Vivi
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