From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/bdw: Cleanup pre prod workarounds Date: Fri, 19 Sep 2014 16:55:56 +0300 Message-ID: <20140919135556.GN12416@intel.com> References: <1411131908-29771-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id EEE0D6E1AA for ; Fri, 19 Sep 2014 06:56:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1411131908-29771-1-git-send-email-mika.kuoppala@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 19, 2014 at 04:05:08PM +0300, Mika Kuoppala wrote: > as these have been fixed in production hw and hurt performance > if applied. > = > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D83482 > Tested-by: zhoujian > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +------------ > 1 file changed, 1 insertion(+), 12 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 681ea86..dfb3bc6 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_= cs *ring) > intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > = > - /* > - * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for > - * pre-production hardware > - */ > intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, > - _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS > - | GEN8_SAMPLER_POWER_BYPASS_DIS)); > - > - intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, > - _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > - > - intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, > - _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); You should adjust the requested ring space too. Looks like this will leave the number of intel_ring_emit_wa() calls even so no need to worry about the QW tail padding quite yet. > = > /* Use Force Non-Coherent whenever executing a 3D context. This is a > * workaround for for a possible hang in the unlikely event a TLB > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC