From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/8] drm/i915: Adds graphic address space
 ballooning logic
Date: Fri, 19 Sep 2014 18:04:22 +0200
Message-ID: <20140919160422.GN15734@phenom.ffwll.local>
References: <1411152428-7226-1-git-send-email-jike.song@intel.com>
 <1411152428-7226-3-git-send-email-jike.song@intel.com>
 <20140919080557.GC21738@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mail-wi0-f170.google.com (mail-wi0-f170.google.com
 [209.85.212.170])
 by gabe.freedesktop.org (Postfix) with ESMTP id 238EF6E6A4
 for <intel-gfx@lists.freedesktop.org>; Fri, 19 Sep 2014 09:03:55 -0700 (PDT)
Received: by mail-wi0-f170.google.com with SMTP id em10so1382705wid.3
 for <intel-gfx@lists.freedesktop.org>; Fri, 19 Sep 2014 09:03:54 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140919080557.GC21738@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, Jike Song <jike.song@intel.com>, daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Sep 19, 2014 at 09:05:57AM +0100, Chris Wilson wrote:
> On Sat, Sep 20, 2014 at 02:47:02AM +0800, Jike Song wrote:
> > From: Yu Zhang <yu.c.zhang@intel.com>
> > If all entries may have prefetch issues,
> > then this special guard page is necessary, to protect unexpected
> > accesses into GTT entries partitioned out by other VMs. Otherwise,
> > we may only need one guard page at the end of the physical GTT space.
> 
> I am a bit dubious how this works when userspace still believes that it
> can access the whole mappable aperture, and then how every driver
> attempts to pin its own planes, rings and whatnot (since it still
> believes that it is talking to the actual hardware and that the hardware
> requires access to its virtual address). The host should be able to move the
> ranges around in order to accommodate userspace in any particular guest
> (hence a balloon interface I presume). But I don't see how that is
> possible, and you don't explain it either.

Yeah this is something we need to fix, either by pimping i915 fault
support to be able to split up a big bo into chunks, or by telling
userspace about the massively reduced contiguous mapping size. It should
be tracked somewhere as a todo task ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch