From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915/bdw: Cleanup pre prod workarounds Date: Tue, 23 Sep 2014 10:20:02 +0200 Message-ID: <20140923082002.GU15734@phenom.ffwll.local> References: <20140919135556.GN12416@intel.com> <1411146326-9884-1-git-send-email-mika.kuoppala@intel.com> <20140919174905.GP12416@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f41.google.com (mail-wg0-f41.google.com [74.125.82.41]) by gabe.freedesktop.org (Postfix) with ESMTP id CC1E46E0B9 for ; Tue, 23 Sep 2014 01:20:06 -0700 (PDT) Received: by mail-wg0-f41.google.com with SMTP id k14so3928774wgh.0 for ; Tue, 23 Sep 2014 01:20:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140919174905.GP12416@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrj=E4l=E4 wrote: > On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote: > > as these have been fixed in production hw and hurt performance > > if applied. > > = > > v2: adjust requested ring space (Ville) > > = > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D83482 > > Tested-by: zhoujian > > Signed-off-by: Mika Kuoppala > = > Documentation agrees that these can go. > Reviewed-by: Ville Syrj=E4l=E4 Cc: stable@vger.kernel.org imo. Jani? -Daniel > = > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++------------- > > 1 file changed, 2 insertions(+), 13 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/= i915/intel_ringbuffer.c > > index 681ea86..679a3c7 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine= _cs *ring) > > * update the number of dwords required based on the > > * actual number of workarounds applied > > */ > > - ret =3D intel_ring_begin(ring, 24); > > + ret =3D intel_ring_begin(ring, 18); > > if (ret) > > return ret; > > = > > @@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engin= e_cs *ring) > > intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, > > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > > = > > - /* > > - * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for > > - * pre-production hardware > > - */ > > intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, > > - _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS > > - | GEN8_SAMPLER_POWER_BYPASS_DIS)); > > - > > - intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, > > - _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > - > > - intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, > > - _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > > + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); > > = > > /* Use Force Non-Coherent whenever executing a 3D context. This is a > > * workaround for for a possible hang in the unlikely event a TLB > > -- = > > 1.9.1 > = > -- = > Ville Syrj=E4l=E4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch