From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default Date: Fri, 26 Sep 2014 22:06:32 +0300 Message-ID: <20140926190632.GF32511@intel.com> References: <1411172190-1642-1-git-send-email-rodrigo.vivi@intel.com> <1411172190-1642-3-git-send-email-rodrigo.vivi@intel.com> <87sijelhbs.fsf@gaia.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 259F46E0D3 for ; Fri, 26 Sep 2014 12:07:07 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87sijelhbs.fsf@gaia.fi.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 26, 2014 at 03:03:19PM +0300, Mika Kuoppala wrote: > Rodrigo Vivi writes: > = > > Program the default initial value of the L3SqcReg1 on BDW for performan= ce > > > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 124ea60..8aafa08 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4821,6 +4821,9 @@ enum punit_power_well { > > #define GEN7_L3SQCREG1 0xB010 > > #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 > > = > > +#define GEN8_L3SQCREG1 0xB100 > > +#define BDW_WA_L3SQCREG1_DEFAULT 0x00610000 > > + > = > This is the default after reset. I think we want 0x00810000 Digging through some attached mails in the hsd I found this number: 0x00784000 This w/a seems to be a real mess. No bspec update, no actual infromation in the w/a db, and even the hsd stuff is more or less useless until you notice there's some attached email dump that has the actual number :( > = > -Mika > = > > #define GEN7_L3CNTLREG1 0xB01C > > #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C > > #define GEN7_L3AGDIS (1<<19) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 1ec3c8f..8a58565 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5811,6 +5811,9 @@ static void broadwell_init_clock_gating(struct dr= m_device *dev) > > I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > > GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > > = > > + /* WaProgramL3SqcReg1Default:bdw */ > > + I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); > > + > = > Should we use intel_ring_emit_wa? > = > -Mika > = > > lpt_init_clock_gating(dev); > > } > > = > > -- = > > 1.9.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC