Re: [PATCH] drm/i915: Flush the PTEs after updating them before suspend

[Daniel Vetter <daniel@ffwll.ch>]

On Thu, Sep 25, 2014 at 10:13:12AM +0100, Chris Wilson wrote:
> As we use WC updates of the PTE, we are responsible for notifying the
> hardware when to flush its TLBs. Do so after we zap all the PTEs before
> suspend (and the BIOS tries to read our GTT).
> 
> Fixes a regression from
> 
> commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
> Author: Ben Widawsky <benjamin.widawsky@intel.com>
> Date:   Wed Oct 16 09:21:30 2013 -0700
> 
>     drm/i915: Disable GGTT PTEs on GEN6+ suspend
> 
> that survived and continue to cause harm even after
> 
> commit e568af1c626031925465a5caaab7cca1303d55c7
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date:   Wed Mar 26 20:08:20 2014 +0100
> 
>     drm/i915: Undo gtt scratch pte unmapping again
> 
> v2: Trivial rebase.
> v3: Fixes requires pointer dances.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82340
> Tested-by: ming.yao@intel.com
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org
> Cc: Takashi Iwai <tiwai@suse.de>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Todd Previte <tprevite@gmail.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1411613f2174..e42925f76b4b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1310,6 +1310,16 @@ void i915_check_and_clear_faults(struct drm_device *dev)
>  	POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
>  }
>  
> +static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
> +{
> +	if (INTEL_INFO(dev_priv->dev)->gen < 6) {
> +		intel_gtt_chipset_flush();
> +	} else {
> +		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> +		POSTING_READ(GFX_FLSH_CNTL_GEN6);
> +	}
> +}
> +
>  void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1326,6 +1336,8 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
>  				       dev_priv->gtt.base.start,
>  				       dev_priv->gtt.base.total,
>  				       true);
> +
> +	i915_ggtt_flush(dev_priv);
>  }
>  
>  void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> @@ -1378,7 +1390,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
>  		gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
>  	}
>  
> -	i915_gem_chipset_flush(dev);
> +	i915_ggtt_flush(dev_priv);
>  }
>  
>  int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
> -- 
> 2.1.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch